From patchwork Fri Jul 1 20:41:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 937652 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p61KgTTk018626 for ; Fri, 1 Jul 2011 20:42:29 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756687Ab1GAUmZ (ORCPT ); Fri, 1 Jul 2011 16:42:25 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:57955 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756648Ab1GAUmX (ORCPT ); Fri, 1 Jul 2011 16:42:23 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p61Kfw1Q014837 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 1 Jul 2011 15:41:58 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep35.itg.ti.com (8.13.7/8.13.8) with ESMTP id p61Kfw2v004634; Fri, 1 Jul 2011 15:41:58 -0500 (CDT) Received: from dlee74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p61KfwgM013917; Fri, 1 Jul 2011 15:41:58 -0500 (CDT) Received: from dlelxv22.itg.ti.com (172.17.1.197) by dlee74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 8.3.106.1; Fri, 1 Jul 2011 15:41:58 -0500 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id p61Kfj6d011169; Fri, 1 Jul 2011 15:41:57 -0500 From: Benoit Cousson To: CC: rnayak@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Benoit Cousson Subject: [PATCH v2 08/18] OMAP4: clock data: Rename clock flags from 443X to 44XX Date: Fri, 1 Jul 2011 22:41:31 +0200 Message-ID: <1309552901-8944-9-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1309552901-8944-1-git-send-email-b-cousson@ti.com> References: <1309552901-8944-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 01 Jul 2011 20:42:30 +0000 (UTC) From: Rajendra Nayak Rename current 4430 definitions to 44XX in oder to make this file applicable for the next revision (OMAP4460). Create new flags for 44XX. They will be extented when OMAP4460 will be introduced. Fix as well the clkdev indentation that were previously broken. Replace a couple of spaces by tabs. Signed-off-by: Rajendra Nayak Signed-off-by: Benoit Cousson Cc: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 663 ++++++++++++------------- arch/arm/plat-omap/include/plat/clkdev_omap.h | 2 + arch/arm/plat-omap/include/plat/clock.h | 1 + 3 files changed, 334 insertions(+), 332 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 9370695..cd8f538 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1,7 +1,7 @@ /* - * OMAP4 Clock data + * OMAP44xx Clock data * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) @@ -127,42 +127,42 @@ static struct clk virt_38400000_ck = { }; static const struct clksel_rate div_1_0_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, + { .div = 1, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_2_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_4430 }, + { .div = 1, .val = 2, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_3_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_4430 }, + { .div = 1, .val = 3, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_4_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_4430 }, + { .div = 1, .val = 4, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_5_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_4430 }, + { .div = 1, .val = 5, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_6_rates[] = { - { .div = 1, .val = 6, .flags = RATE_IN_4430 }, + { .div = 1, .val = 6, .flags = RATE_IN_44XX }, { .div = 0 }, }; static const struct clksel_rate div_1_7_rates[] = { - { .div = 1, .val = 7, .flags = RATE_IN_4430 }, + { .div = 1, .val = 7, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -285,37 +285,37 @@ static struct clk dpll_abe_x2_ck = { }; static const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 2, .val = 2, .flags = RATE_IN_4430 }, - { .div = 3, .val = 3, .flags = RATE_IN_4430 }, - { .div = 4, .val = 4, .flags = RATE_IN_4430 }, - { .div = 5, .val = 5, .flags = RATE_IN_4430 }, - { .div = 6, .val = 6, .flags = RATE_IN_4430 }, - { .div = 7, .val = 7, .flags = RATE_IN_4430 }, - { .div = 8, .val = 8, .flags = RATE_IN_4430 }, - { .div = 9, .val = 9, .flags = RATE_IN_4430 }, - { .div = 10, .val = 10, .flags = RATE_IN_4430 }, - { .div = 11, .val = 11, .flags = RATE_IN_4430 }, - { .div = 12, .val = 12, .flags = RATE_IN_4430 }, - { .div = 13, .val = 13, .flags = RATE_IN_4430 }, - { .div = 14, .val = 14, .flags = RATE_IN_4430 }, - { .div = 15, .val = 15, .flags = RATE_IN_4430 }, - { .div = 16, .val = 16, .flags = RATE_IN_4430 }, - { .div = 17, .val = 17, .flags = RATE_IN_4430 }, - { .div = 18, .val = 18, .flags = RATE_IN_4430 }, - { .div = 19, .val = 19, .flags = RATE_IN_4430 }, - { .div = 20, .val = 20, .flags = RATE_IN_4430 }, - { .div = 21, .val = 21, .flags = RATE_IN_4430 }, - { .div = 22, .val = 22, .flags = RATE_IN_4430 }, - { .div = 23, .val = 23, .flags = RATE_IN_4430 }, - { .div = 24, .val = 24, .flags = RATE_IN_4430 }, - { .div = 25, .val = 25, .flags = RATE_IN_4430 }, - { .div = 26, .val = 26, .flags = RATE_IN_4430 }, - { .div = 27, .val = 27, .flags = RATE_IN_4430 }, - { .div = 28, .val = 28, .flags = RATE_IN_4430 }, - { .div = 29, .val = 29, .flags = RATE_IN_4430 }, - { .div = 30, .val = 30, .flags = RATE_IN_4430 }, - { .div = 31, .val = 31, .flags = RATE_IN_4430 }, + { .div = 1, .val = 1, .flags = RATE_IN_44XX }, + { .div = 2, .val = 2, .flags = RATE_IN_44XX }, + { .div = 3, .val = 3, .flags = RATE_IN_44XX }, + { .div = 4, .val = 4, .flags = RATE_IN_44XX }, + { .div = 5, .val = 5, .flags = RATE_IN_44XX }, + { .div = 6, .val = 6, .flags = RATE_IN_44XX }, + { .div = 7, .val = 7, .flags = RATE_IN_44XX }, + { .div = 8, .val = 8, .flags = RATE_IN_44XX }, + { .div = 9, .val = 9, .flags = RATE_IN_44XX }, + { .div = 10, .val = 10, .flags = RATE_IN_44XX }, + { .div = 11, .val = 11, .flags = RATE_IN_44XX }, + { .div = 12, .val = 12, .flags = RATE_IN_44XX }, + { .div = 13, .val = 13, .flags = RATE_IN_44XX }, + { .div = 14, .val = 14, .flags = RATE_IN_44XX }, + { .div = 15, .val = 15, .flags = RATE_IN_44XX }, + { .div = 16, .val = 16, .flags = RATE_IN_44XX }, + { .div = 17, .val = 17, .flags = RATE_IN_44XX }, + { .div = 18, .val = 18, .flags = RATE_IN_44XX }, + { .div = 19, .val = 19, .flags = RATE_IN_44XX }, + { .div = 20, .val = 20, .flags = RATE_IN_44XX }, + { .div = 21, .val = 21, .flags = RATE_IN_44XX }, + { .div = 22, .val = 22, .flags = RATE_IN_44XX }, + { .div = 23, .val = 23, .flags = RATE_IN_44XX }, + { .div = 24, .val = 24, .flags = RATE_IN_44XX }, + { .div = 25, .val = 25, .flags = RATE_IN_44XX }, + { .div = 26, .val = 26, .flags = RATE_IN_44XX }, + { .div = 27, .val = 27, .flags = RATE_IN_44XX }, + { .div = 28, .val = 28, .flags = RATE_IN_44XX }, + { .div = 29, .val = 29, .flags = RATE_IN_44XX }, + { .div = 30, .val = 30, .flags = RATE_IN_44XX }, + { .div = 31, .val = 31, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -345,9 +345,9 @@ static struct clk abe_24m_fclk = { }; static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_44XX }, + { .div = 2, .val = 1, .flags = RATE_IN_44XX }, + { .div = 4, .val = 2, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -369,8 +369,8 @@ static struct clk abe_clk = { }; static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_44XX }, + { .div = 2, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -542,10 +542,10 @@ static struct clk div_core_ck = { }; static const struct clksel_rate div4_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 8, .val = 3, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_44XX }, + { .div = 2, .val = 1, .flags = RATE_IN_44XX }, + { .div = 4, .val = 2, .flags = RATE_IN_44XX }, + { .div = 8, .val = 3, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -1100,8 +1100,8 @@ static struct clk func_24mc_fclk = { }; static const struct clksel_rate div2_4to8_rates[] = { - { .div = 4, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, + { .div = 4, .val = 0, .flags = RATE_IN_44XX }, + { .div = 8, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -1131,8 +1131,8 @@ static struct clk func_48mc_fclk = { }; static const struct clksel_rate div2_2to4_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 4, .val = 1, .flags = RATE_IN_4430 }, + { .div = 2, .val = 0, .flags = RATE_IN_44XX }, + { .div = 4, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -1184,8 +1184,8 @@ static struct clk hsmmc6_fclk = { }; static const struct clksel_rate div2_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_44XX }, + { .div = 8, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -2753,8 +2753,8 @@ static struct clk usb_tll_hs_ick = { }; static const struct clksel_rate div2_14to18_rates[] = { - { .div = 14, .val = 0, .flags = RATE_IN_4430 }, - { .div = 18, .val = 1, .flags = RATE_IN_4430 }, + { .div = 14, .val = 0, .flags = RATE_IN_44XX }, + { .div = 18, .val = 1, .flags = RATE_IN_44XX }, { .div = 0 }, }; @@ -2815,7 +2815,6 @@ static struct clk wd_timer3_fck = { .recalc = &followparent_recalc, }; -/* Remaining optional clocks */ static const struct clksel stm_clk_div_div[] = { { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -2952,7 +2951,7 @@ static struct clk auxclkreq0_ck = { .parent = &auxclk0_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -2963,7 +2962,7 @@ static struct clk auxclkreq1_ck = { .parent = &auxclk1_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -2974,7 +2973,7 @@ static struct clk auxclkreq2_ck = { .parent = &auxclk2_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -2985,7 +2984,7 @@ static struct clk auxclkreq3_ck = { .parent = &auxclk3_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -2996,7 +2995,7 @@ static struct clk auxclkreq4_ck = { .parent = &auxclk4_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -3007,7 +3006,7 @@ static struct clk auxclkreq5_ck = { .parent = &auxclk5_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, - .clksel = auxclkreq_sel, + .clksel = auxclkreq_sel, .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, .clksel_mask = OMAP4_MAPPING_MASK, .recalc = &omap2_clksel_recalc, @@ -3018,279 +3017,279 @@ static struct clk auxclkreq5_ck = { */ static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), - CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), - CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), - CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), - CLK(NULL, "abe_clk", &abe_clk, CK_443X), - CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), - CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), - CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), - CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), - CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), - CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), - CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), - CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), - CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), - CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), - CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), - CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), - CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), - CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), - CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), - CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), - CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), - CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), - CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), - CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), - CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), - CLK("omapdss_dss", "ick", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), - CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), - CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), - CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), - CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), - CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), - CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), - CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), - CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), - CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), - CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), - CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), - CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), - CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), - CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), - CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), - CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), - CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), - CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), - CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_44XX), + CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_44XX), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_44XX), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_44XX), + CLK(NULL, "slimbus_clk", &slimbus_clk, CK_44XX), + CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_44XX), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_44XX), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_44XX), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_44XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_44XX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_44XX), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_44XX), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_44XX), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_44XX), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_44XX), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_44XX), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_44XX), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_44XX), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_44XX), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_44XX), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_44XX), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_44XX), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_44XX), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_44XX), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_44XX), + CLK(NULL, "abe_clk", &abe_clk, CK_44XX), + CLK(NULL, "aess_fclk", &aess_fclk, CK_44XX), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_44XX), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_44XX), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_44XX), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_44XX), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_44XX), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_44XX), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_44XX), + CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_44XX), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_44XX), + CLK(NULL, "div_core_ck", &div_core_ck, CK_44XX), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_44XX), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_44XX), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_44XX), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_44XX), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_44XX), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_44XX), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_44XX), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_44XX), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_44XX), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_44XX), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_44XX), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_44XX), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_44XX), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_44XX), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_44XX), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_44XX), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_44XX), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_44XX), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_44XX), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_44XX), + CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_44XX), + CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_44XX), + CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_44XX), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_44XX), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_44XX), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_44XX), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_44XX), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_44XX), + CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_44XX), + CLK(NULL, "func_24m_clk", &func_24m_clk, CK_44XX), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_44XX), + CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_44XX), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_44XX), + CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_44XX), + CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_44XX), + CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_44XX), + CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_44XX), + CLK(NULL, "l3_div_ck", &l3_div_ck, CK_44XX), + CLK(NULL, "l4_div_ck", &l4_div_ck, CK_44XX), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_44XX), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_44XX), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_44XX), + CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_44XX), + CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_44XX), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_44XX), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_44XX), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_44XX), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_44XX), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_44XX), + CLK(NULL, "aes1_fck", &aes1_fck, CK_44XX), + CLK(NULL, "aes2_fck", &aes2_fck, CK_44XX), + CLK(NULL, "aess_fck", &aess_fck, CK_44XX), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_44XX), + CLK(NULL, "des3des_fck", &des3des_fck, CK_44XX), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_44XX), + CLK(NULL, "dmic_fck", &dmic_fck, CK_44XX), + CLK(NULL, "dsp_fck", &dsp_fck, CK_44XX), + CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_44XX), + CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_44XX), + CLK("omapdss_dss", "fck", &dss_dss_clk, CK_44XX), + CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_44XX), + CLK("omapdss_dss", "ick", &dss_fck, CK_44XX), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_44XX), + CLK(NULL, "emif1_fck", &emif1_fck, CK_44XX), + CLK(NULL, "emif2_fck", &emif2_fck, CK_44XX), + CLK(NULL, "fdif_fck", &fdif_fck, CK_44XX), + CLK(NULL, "fpka_fck", &fpka_fck, CK_44XX), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_44XX), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_44XX), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_44XX), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_44XX), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_44XX), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_44XX), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_44XX), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_44XX), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_44XX), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_44XX), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_44XX), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_44XX), + CLK(NULL, "gpmc_ick", &gpmc_ick, CK_44XX), + CLK(NULL, "gpu_fck", &gpu_fck, CK_44XX), + CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_44XX), + CLK(NULL, "hsi_fck", &hsi_fck, CK_44XX), + CLK("omap_i2c.1", "fck", &i2c1_fck, CK_44XX), + CLK("omap_i2c.2", "fck", &i2c2_fck, CK_44XX), + CLK("omap_i2c.3", "fck", &i2c3_fck, CK_44XX), + CLK("omap_i2c.4", "fck", &i2c4_fck, CK_44XX), + CLK(NULL, "ipu_fck", &ipu_fck, CK_44XX), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_44XX), + CLK(NULL, "iss_fck", &iss_fck, CK_44XX), + CLK(NULL, "iva_fck", &iva_fck, CK_44XX), + CLK(NULL, "kbd_fck", &kbd_fck, CK_44XX), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_44XX), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_44XX), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_44XX), + CLK(NULL, "mcasp_fck", &mcasp_fck, CK_44XX), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_44XX), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_44XX), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_44XX), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_44XX), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_44XX), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_44XX), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_44XX), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_44XX), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_44XX), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_44XX), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_44XX), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_44XX), + CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_44XX), + CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_44XX), + CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_44XX), + CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_44XX), + CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_44XX), + CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_44XX), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_44XX), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_44XX), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_44XX), + CLK("omap_rng", "ick", &rng_ick, CK_44XX), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_44XX), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_44XX), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_44XX), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_44XX), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_44XX), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_44XX), + CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_44XX), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_44XX), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_44XX), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_44XX), + CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_44XX), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_44XX), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_44XX), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_44XX), + CLK(NULL, "gpt1_fck", &timer1_fck, CK_44XX), + CLK(NULL, "gpt10_fck", &timer10_fck, CK_44XX), + CLK(NULL, "gpt11_fck", &timer11_fck, CK_44XX), + CLK(NULL, "gpt2_fck", &timer2_fck, CK_44XX), + CLK(NULL, "gpt3_fck", &timer3_fck, CK_44XX), + CLK(NULL, "gpt4_fck", &timer4_fck, CK_44XX), + CLK(NULL, "gpt5_fck", &timer5_fck, CK_44XX), + CLK(NULL, "gpt6_fck", &timer6_fck, CK_44XX), + CLK(NULL, "gpt7_fck", &timer7_fck, CK_44XX), + CLK(NULL, "gpt8_fck", &timer8_fck, CK_44XX), + CLK(NULL, "gpt9_fck", &timer9_fck, CK_44XX), + CLK(NULL, "uart1_fck", &uart1_fck, CK_44XX), + CLK(NULL, "uart2_fck", &uart2_fck, CK_44XX), + CLK(NULL, "uart3_fck", &uart3_fck, CK_44XX), + CLK(NULL, "uart4_fck", &uart4_fck, CK_44XX), + CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_44XX), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_44XX), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_44XX), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_44XX), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_44XX), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_44XX), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_44XX), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_44XX), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_44XX), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_44XX), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_44XX), + CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_44XX), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_44XX), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_44XX), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_44XX), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_44XX), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_44XX), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_44XX), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_44XX), + CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_44XX), + CLK(NULL, "usim_ck", &usim_ck, CK_44XX), + CLK(NULL, "usim_fclk", &usim_fclk, CK_44XX), + CLK(NULL, "usim_fck", &usim_fck, CK_44XX), + CLK("omap_wdt", "fck", &wd_timer2_fck, CK_44XX), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_44XX), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_44XX), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_44XX), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_44XX), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_44XX), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_44XX), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_44XX), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_44XX), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_44XX), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_44XX), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_44XX), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_44XX), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_44XX), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_44XX), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_44XX), + CLK(NULL, "gpmc_ck", &dummy_ck, CK_44XX), + CLK(NULL, "gpt1_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt2_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt3_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt4_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt5_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt6_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt7_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt8_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt9_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt10_ick", &dummy_ck, CK_44XX), + CLK(NULL, "gpt11_ick", &dummy_ck, CK_44XX), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_44XX), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_44XX), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_44XX), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_44XX), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_44XX), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_44XX), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_44XX), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_44XX), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_44XX), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_44XX), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_44XX), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_44XX), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_44XX), + CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_44XX), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_44XX), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_44XX), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_44XX), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_44XX), + CLK(NULL, "uart1_ick", &dummy_ck, CK_44XX), + CLK(NULL, "uart2_ick", &dummy_ck, CK_44XX), + CLK(NULL, "uart3_ick", &dummy_ck, CK_44XX), + CLK(NULL, "uart4_ick", &dummy_ck, CK_44XX), + CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_44XX), + CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_44XX), + CLK("omap_wdt", "ick", &dummy_ck, CK_44XX), }; int __init omap4xxx_clk_init(void) { struct omap_clk *c; - u32 cpu_clkflg; + u32 cpu_clkflg = 0; - if (cpu_is_omap44xx()) { + if (cpu_is_omap443x()) { cpu_mask = RATE_IN_4430; cpu_clkflg = CK_443X; } diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index f1899a3..4609a3f 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -39,11 +39,13 @@ struct omap_clk { #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) +#define CK_446X (1 << 13) #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) +#define CK_44XX (CK_443X) #endif diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index f57e064..10349fe 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -62,6 +62,7 @@ struct clkops { #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) +#define RATE_IN_44XX (RATE_IN_4430) /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)