From patchwork Wed Jul 13 22:06:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: manjugk manjugk X-Patchwork-Id: 973512 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6DLmbnH002261 for ; Wed, 13 Jul 2011 21:48:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752259Ab1GMVsq (ORCPT ); Wed, 13 Jul 2011 17:48:46 -0400 Received: from [117.192.79.57] ([117.192.79.57]:44974 "EHLO manju-desktop" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752245Ab1GMVsp (ORCPT ); Wed, 13 Jul 2011 17:48:45 -0400 To: devicetree-discuss@lists.ozlabs.org Date: Thu, 14 Jul 2011 03:06:12 +0500 Subject: [PATCH 1/4] dt: omap3: add SoC file for handling i2c controllers Envelope-To: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, grant.likely@secretlab.ca, ben-linux@fluff.org References: <1310592975-25773-1-git-send-email-manjugk@ti.com> CC: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, grant.likely@secretlab.ca, ben-linux@fluff.org Message-ID: <1310592975-25773-2-git-send-email-manjugk@ti.com> From: "G, Manjunath Kondaiah" Received: from manju-desktop (Citadel from userid 1000) by manju-desktop; Thu, 14 Jul 2011 03:06:16 +0500 X-Mailer: git-send-email 1.7.4.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 13 Jul 2011 21:48:52 +0000 (UTC) Add omap3 SoC file for handling omap3 SoC i2c controllers existing on l4-core bus. Out of three i2c controllers, first i2c controller is interfaced with PMIC on all the boards of OMAP3. The clock for i2c controllers are controlled through omap hwmod framework hence first i2c controller device registration through dt is disabled till hwmod dependencies are resolved. Signed-off-by: G, Manjunath Kondaiah --- arch/arm/boot/dts/omap3-soc.dtsi | 65 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 arch/arm/boot/dts/omap3-soc.dtsi diff --git a/arch/arm/boot/dts/omap3-soc.dtsi b/arch/arm/boot/dts/omap3-soc.dtsi new file mode 100644 index 0000000..f186a32 --- /dev/null +++ b/arch/arm/boot/dts/omap3-soc.dtsi @@ -0,0 +1,65 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "ti,omap3"; + compatible = "ti,omap3"; + + intc: interrupt-controller@0x48200000 { + compatible = "ti,omap3-intc", "arm,intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + l4-core { + compatible = "ti,l4-core"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,omap3-i2c"; + reg = <0x70000 0x100>; + interrupts = < 88 >; + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,omap3-i2c"; + reg = <0x72000 0x100>; + interrupts = < 89 >; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,omap3-i2c"; + reg = <0x60000 0x100>; + interrupts = < 93 >; + }; + }; + + l4-per { + compatible = "ti,l4-per"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x49000000 0x100000>; + }; +};