From patchwork Thu Jul 14 23:24:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 976842 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6ENOVAN001918 for ; Thu, 14 Jul 2011 23:24:31 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932580Ab1GNXYa (ORCPT ); Thu, 14 Jul 2011 19:24:30 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:45312 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932558Ab1GNXY3 (ORCPT ); Thu, 14 Jul 2011 19:24:29 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6ENOSxE000461 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 14 Jul 2011 18:24:28 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6ENOSxS019738; Thu, 14 Jul 2011 18:24:28 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6ENOSH3014794; Thu, 14 Jul 2011 18:24:28 -0500 (CDT) Received: from dlelxv23.itg.ti.com (172.17.1.198) by DLEE73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.3.106.1; Thu, 14 Jul 2011 18:24:28 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6ENORih016604; Thu, 14 Jul 2011 18:24:27 -0500 Received: from localhost (h1-7.vpn.ti.com [172.24.1.7]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id p6ENORf08254; Thu, 14 Jul 2011 18:24:27 -0500 (CDT) From: Jon Hunter To: Paul Walmsley CC: linux-omap , Jon Hunter Subject: [PATCH 1/6] OMAP4: Add missing clock divider for OCP_ABE_ICLK Date: Thu, 14 Jul 2011 18:24:25 -0500 Message-ID: <1310685865-3249-1-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Jul 2011 23:24:31 +0000 (UTC) From: Jon Hunter The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the parent clock of the AESS_FCLK is the ABE_FCLK... ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which determine their operational frequency. However, the dividers for the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 and the OCP_ABE_ICLK is 1. The above relationship between the AESS_FCLK and OCP_ABE_ICLK dividers ensure that the OCP_ABE_ICLK clock is always half the frequency of the ABE_CLK... OCP_ABE_ICLK = ABE_FCLK/2 The divider for the OCP_ABE_ICLK is currently missing so add a divider that will ensure the OCP_ABE_ICLK frequency is always half the ABE_FCLK frequency. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/clock44xx_data.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8c96567..6e158ce 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1301,11 +1301,25 @@ static struct clk mcasp3_fclk = { .recalc = &followparent_recalc, }; +static const struct clksel_rate div2_2to1_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_4430 }, + { .div = 2, .val = 0, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static const struct clksel ocp_abe_iclk_div[] = { + { .parent = &aess_fclk, .rates = div2_2to1_rates }, + { .parent = NULL }, +}; + static struct clk ocp_abe_iclk = { .name = "ocp_abe_iclk", .parent = &aess_fclk, + .clksel = ocp_abe_iclk_div, + .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, .ops = &clkops_null, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, }; static struct clk per_abe_24m_fclk = {