diff mbox

[v14,REPOST,11/12] OMAP: dmtimer: add context save/restore routines

Message ID 1310731501-13078-12-git-send-email-tarun.kanti@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tarun Kanti DebBarma July 15, 2011, 12:05 p.m. UTC
Define context register structure and make it member of struct omap_dm_timer.
Also define two routines to save and restore dmtimer context to be used
subsequently.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
 arch/arm/plat-omap/dmtimer.c              |   48 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/dmtimer.h |   24 ++++++++++++++
 2 files changed, 72 insertions(+), 0 deletions(-)

Comments

Santosh Shilimkar Aug. 26, 2011, 3:46 p.m. UTC | #1
On Friday 15 July 2011 05:35 PM, Tarun Kanti DebBarma wrote:
> Define context register structure and make it member of struct omap_dm_timer.
> Also define two routines to save and restore dmtimer context to be used
> subsequently.
>
> Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com>
> ---
>   arch/arm/plat-omap/dmtimer.c              |   48 +++++++++++++++++++++++++++++
>   arch/arm/plat-omap/include/plat/dmtimer.h |   24 ++++++++++++++
>   2 files changed, 72 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 8c8cb00..cdef48b 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -87,6 +87,54 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
>   				timer->func_offset);
>   }
>
> +static void omap_timer_save_context(struct omap_dm_timer *timer)
> +{
> +	timer->context.tiocp_cfg =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
> +	timer->context.tistat =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG);
> +	timer->context.tisr =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
> +	timer->context.tier =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG);
> +	timer->context.twer =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
> +	timer->context.tclr =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> +	timer->context.tcrr =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
> +	timer->context.tldr =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
> +	timer->context.tmar =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
> +	timer->context.tsicr =
> +		omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
> +}
> +
> +static void omap_timer_restore_context(struct omap_dm_timer *timer)
> +{
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG,
> +				timer->context.tiocp_cfg);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_SYS_STAT_REG,
> +				timer->context.tistat);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
> +				timer->context.tisr);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG,
> +				timer->context.tier);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
> +				timer->context.twer);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
> +				timer->context.tclr);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
> +				timer->context.tcrr);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
> +				timer->context.tldr);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
> +				timer->context.tmar);
> +	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
> +				timer->context.tsicr);
> +}
> +
Looks good.
Take care of ordering of the restore code similar to
GPIO code.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Regards
Santosh
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diff mbox

Patch

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 8c8cb00..cdef48b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -87,6 +87,54 @@  static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
 				timer->func_offset);
 }
 
+static void omap_timer_save_context(struct omap_dm_timer *timer)
+{
+	timer->context.tiocp_cfg =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
+	timer->context.tistat =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG);
+	timer->context.tisr =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
+	timer->context.tier =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG);
+	timer->context.twer =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
+	timer->context.tclr =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+	timer->context.tcrr =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
+	timer->context.tldr =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
+	timer->context.tmar =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
+	timer->context.tsicr =
+		omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
+}
+
+static void omap_timer_restore_context(struct omap_dm_timer *timer)
+{
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG,
+				timer->context.tiocp_cfg);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_SYS_STAT_REG,
+				timer->context.tistat);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+				timer->context.tisr);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG,
+				timer->context.tier);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
+				timer->context.twer);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
+				timer->context.tclr);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
+				timer->context.tcrr);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
+				timer->context.tldr);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
+				timer->context.tmar);
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+				timer->context.tsicr);
+}
+
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 {
 	int c;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 6e34094..9a2d7e3 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -234,6 +234,29 @@  int omap_dm_timers_active(void);
 
 #define MAX_WRITE_PEND_WAIT            10000 /* 10ms timeout delay */
 
+struct timer_regs {
+	u32 tidr;
+	u32 tiocp_cfg;
+	u32 tistat;
+	u32 tisr;
+	u32 tier;
+	u32 twer;
+	u32 tclr;
+	u32 tcrr;
+	u32 tldr;
+	u32 ttrg;
+	u32 twps;
+	u32 tmar;
+	u32 tcar1;
+	u32 tsicr;
+	u32 tcar2;
+	u32 tpir;
+	u32 tnir;
+	u32 tcvr;
+	u32 tocr;
+	u32 towr;
+};
+
 struct omap_dm_timer {
 	unsigned long phys_base;
 	int id;
@@ -245,6 +268,7 @@  struct omap_dm_timer {
 	unsigned posted:1;
 	u8 func_offset;
 	u8 intr_offset;
+	struct timer_regs context;
 	struct platform_device *pdev;
 	struct list_head node;
 };