From patchwork Fri Jul 15 12:05:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 978102 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6FC5Y5B001967 for ; Fri, 15 Jul 2011 12:06:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751226Ab1GOMGI (ORCPT ); Fri, 15 Jul 2011 08:06:08 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:34044 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019Ab1GOMGH (ORCPT ); Fri, 15 Jul 2011 08:06:07 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6FC61ru021009 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 15 Jul 2011 07:06:01 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep34.itg.ti.com (8.13.7/8.13.8) with ESMTP id p6FC61GC000863; Fri, 15 Jul 2011 07:06:01 -0500 (CDT) Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6FC4iUK000294; Fri, 15 Jul 2011 07:06:00 -0500 (CDT) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Fri, 15 Jul 2011 17:35:29 +0530 Received: from localhost.localdomain ([172.24.190.145]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6FC51Zi017050; Fri, 15 Jul 2011 17:35:26 +0530 (IST) From: Tarun Kanti DebBarma To: CC: , , , , Tarun Kanti DebBarma Subject: [PATCH v14 REPOST 11/12] OMAP: dmtimer: add context save/restore routines Date: Fri, 15 Jul 2011 17:35:00 +0530 Message-ID: <1310731501-13078-12-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1310731501-13078-1-git-send-email-tarun.kanti@ti.com> References: <1310731501-13078-1-git-send-email-tarun.kanti@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 15 Jul 2011 12:06:35 +0000 (UTC) Define context register structure and make it member of struct omap_dm_timer. Also define two routines to save and restore dmtimer context to be used subsequently. Signed-off-by: Tarun Kanti DebBarma Reviewed-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 48 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 24 ++++++++++++++ 2 files changed, 72 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 8c8cb00..cdef48b 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -87,6 +87,54 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, timer->func_offset); } +static void omap_timer_save_context(struct omap_dm_timer *timer) +{ + timer->context.tiocp_cfg = + omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); + timer->context.tistat = + omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG); + timer->context.tisr = + omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); + timer->context.tier = + omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG); + timer->context.twer = + omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); + timer->context.tclr = + omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + timer->context.tcrr = + omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); + timer->context.tldr = + omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); + timer->context.tmar = + omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); + timer->context.tsicr = + omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); +} + +static void omap_timer_restore_context(struct omap_dm_timer *timer) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, + timer->context.tiocp_cfg); + omap_dm_timer_write_reg(timer, OMAP_TIMER_SYS_STAT_REG, + timer->context.tistat); + omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, + timer->context.tisr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, + timer->context.tier); + omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, + timer->context.twer); + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, + timer->context.tclr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, + timer->context.tcrr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, + timer->context.tldr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, + timer->context.tmar); + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, + timer->context.tsicr); +} + static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) { int c; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 6e34094..9a2d7e3 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -234,6 +234,29 @@ int omap_dm_timers_active(void); #define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */ +struct timer_regs { + u32 tidr; + u32 tiocp_cfg; + u32 tistat; + u32 tisr; + u32 tier; + u32 twer; + u32 tclr; + u32 tcrr; + u32 tldr; + u32 ttrg; + u32 twps; + u32 tmar; + u32 tcar1; + u32 tsicr; + u32 tcar2; + u32 tpir; + u32 tnir; + u32 tcvr; + u32 tocr; + u32 towr; +}; + struct omap_dm_timer { unsigned long phys_base; int id; @@ -245,6 +268,7 @@ struct omap_dm_timer { unsigned posted:1; u8 func_offset; u8 intr_offset; + struct timer_regs context; struct platform_device *pdev; struct list_head node; };