From patchwork Mon Jul 25 16:36:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 1005522 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6PGabsW000371 for ; Mon, 25 Jul 2011 16:36:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752490Ab1GYQgh (ORCPT ); Mon, 25 Jul 2011 12:36:37 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55963 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752458Ab1GYQgg convert rfc822-to-8bit (ORCPT ); Mon, 25 Jul 2011 12:36:36 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6PGaZJh016124 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 25 Jul 2011 11:36:35 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6PGaZEK007471 for ; Mon, 25 Jul 2011 11:36:35 -0500 (CDT) Received: from dnce72.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6PGaYCN009317 for ; Mon, 25 Jul 2011 11:36:35 -0500 (CDT) thread-index: AcxK6QSTYYcpXl7NStqJ9ElqopYPSA== Content-Class: urn:content-classes:message Importance: normal X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.4657 Received: from localhost.localdomain (172.24.88.14) by dnce72.ent.ti.com (137.167.131.87) with Microsoft SMTP Server (TLS) id 8.3.106.1; Mon, 25 Jul 2011 18:36:34 +0200 From: Tero Kristo To: Subject: [PATCHv6 07/11] TEMP: serial: added mux support Date: Mon, 25 Jul 2011 19:36:07 +0300 Message-ID: <1311611771-15093-8-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1311611771-15093-1-git-send-email-t-kristo@ti.com> References: <1311611771-15093-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 25 Jul 2011 16:36:38 +0000 (UTC) Just for PRCM chain handler testing purposes. This should be replaced with a proper implementation. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/serial.c | 71 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 69 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 651fb91..47c4353 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -852,17 +852,84 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) * can call this function when they want to have default behaviour * for serial ports (e.g initialize them all as serial ports). */ + +struct serial_mux_conf { + char *name; + int omap3_mux; + int omap4_mux; +}; + +#define OMAP3_SERIAL_MUX_IN_PU (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0) +#define OMAP3_SERIAL_MUX_IN_PD (OMAP_PIN_INPUT_PULLDOWN | OMAP_MUX_MODE0) +#define OMAP3_SERIAL_MUX_IN (OMAP_PIN_INPUT | OMAP_MUX_MODE0) +#define OMAP3_SERIAL_MUX_OUT (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0) +#define OMAP4_SERIAL_MUX_IN_PU (OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0) +#define OMAP4_SERIAL_MUX_OUT (OMAP_PIN_OUTPUT | OMAP_MUX_MODE0) +#define OMAP4_SERIAL_MUX_IN (OMAP_PIN_INPUT | OMAP_MUX_MODE0) +#define SERIAL_DISABLED OMAP_MUX_MODE7 + +#define OMAP_SERIAL_NUM_PADS_PER_PORT 4 + +static const struct serial_mux_conf serial_mux_data[] = { + { "uart1_cts.uart1_cts", OMAP3_SERIAL_MUX_IN, SERIAL_DISABLED, }, + { "uart1_rts.uart1_rts", OMAP3_SERIAL_MUX_OUT, SERIAL_DISABLED, }, + { "uart1_rx.uart1_rx", OMAP3_SERIAL_MUX_IN, SERIAL_DISABLED, }, + { "uart1_tx.uart1_tx", OMAP3_SERIAL_MUX_OUT, SERIAL_DISABLED, }, + { "uart2_cts.uart2_cts", OMAP3_SERIAL_MUX_IN, + OMAP4_SERIAL_MUX_IN_PU, }, + { "uart2_rts.uart2_rts", OMAP3_SERIAL_MUX_OUT, OMAP4_SERIAL_MUX_OUT, }, + { "uart2_rx.uart2_rx", OMAP3_SERIAL_MUX_IN, OMAP4_SERIAL_MUX_IN_PU, }, + { "uart2_tx.uart2_tx", OMAP3_SERIAL_MUX_OUT, OMAP4_SERIAL_MUX_OUT }, + { "uart3_cts_rctx.uart3_cts_rctx", OMAP3_SERIAL_MUX_IN_PD, + OMAP4_SERIAL_MUX_IN_PU, }, + { "uart3_rts_sd.uart3_rts_sd", OMAP3_SERIAL_MUX_OUT, + OMAP4_SERIAL_MUX_OUT, }, + { "uart3_rx_irrx.uart3_rx_irrx", OMAP3_SERIAL_MUX_IN, + OMAP4_SERIAL_MUX_IN, }, + { "uart3_tx_irtx.uart3_tx_irtx", OMAP3_SERIAL_MUX_OUT, + OMAP4_SERIAL_MUX_OUT, }, + { "uart4_rx.uart4_rx", SERIAL_DISABLED, OMAP4_SERIAL_MUX_IN, }, + { "uart4_tx.uart4_tx", SERIAL_DISABLED, OMAP4_SERIAL_MUX_OUT, }, + { NULL, 0, 0, }, + { NULL, 0, 0, }, +}; + void __init omap_serial_init(void) { struct omap_uart_state *uart; struct omap_board_data bdata; + struct omap_device_pad *pads; + int idx; + int i; + pads = kmalloc(sizeof(struct omap_device_pad) * 4, GFP_KERNEL); list_for_each_entry(uart, &uart_list, node) { bdata.id = uart->num; bdata.flags = 0; - bdata.pads = NULL; bdata.pads_cnt = 0; + bdata.pads = pads; + + for (i = 0; i < OMAP_SERIAL_NUM_PADS_PER_PORT; i++) { + idx = bdata.id * OMAP_SERIAL_NUM_PADS_PER_PORT + i; + pads[i].name = serial_mux_data[idx].name; + pads[i].enable = 0; + pads[i].idle = 0; + pads[i].flags = 0; + if (cpu_is_omap34xx()) + pads[i].enable = serial_mux_data[idx].omap3_mux; + if (cpu_is_omap44xx()) + pads[i].enable = serial_mux_data[idx].omap4_mux; + if (pads[i].enable != SERIAL_DISABLED) + bdata.pads_cnt++; + if (pads[i].enable & OMAP_PIN_INPUT) { + pads[i].flags = OMAP_DEVICE_PAD_REMUX | + OMAP_DEVICE_PAD_WAKEUP; + } + pads[i].idle = pads[i].enable; + } + if (bdata.pads_cnt == 0) + bdata.pads = NULL; omap_serial_init_port(&bdata); - } + kfree(pads); }