From patchwork Tue Aug 23 12:28:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1088282 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7NCSbAZ002050 for ; Tue, 23 Aug 2011 12:28:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753362Ab1HWM2i (ORCPT ); Tue, 23 Aug 2011 08:28:38 -0400 Received: from na3sys009aog107.obsmtp.com ([74.125.149.197]:60082 "EHLO na3sys009aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752273Ab1HWM2h (ORCPT ); Tue, 23 Aug 2011 08:28:37 -0400 Received: from mail-bw0-f54.google.com ([209.85.214.54]) (using TLSv1) by na3sys009aob107.postini.com ([74.125.148.12]) with SMTP ID DSNKTlOc9HjjrpHHKogi7n11maBQDrY+jqI2@postini.com; Tue, 23 Aug 2011 05:28:37 PDT Received: by mail-bw0-f54.google.com with SMTP id t8so42574bka.41 for ; Tue, 23 Aug 2011 05:28:36 -0700 (PDT) Received: by 10.204.134.13 with SMTP id h13mr1559918bkt.350.1314102516200; Tue, 23 Aug 2011 05:28:36 -0700 (PDT) Received: from localhost.localdomain (a62-248-128-208.elisa-laajakaista.fi [62.248.128.208]) by mx.google.com with ESMTPS id v22sm49449bkw.12.2011.08.23.05.28.33 (version=SSLv3 cipher=OTHER); Tue, 23 Aug 2011 05:28:35 -0700 (PDT) From: Tomi Valkeinen To: linux-omap@vger.kernel.org, paul@pwsan.com, linux-arm-kernel@lists.infradead.org Cc: Tomi Valkeinen Subject: [PATCH 1/9] OMAP2xxx: HWMOD: Fix DSS reset Date: Tue, 23 Aug 2011 15:28:11 +0300 Message-Id: <1314102499-30407-2-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314102499-30407-1-git-send-email-tomi.valkeinen@ti.com> References: <1314102499-30407-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 23 Aug 2011 12:28:38 +0000 (UTC) DSS needs all DSS clocks to be enabled to be able to finish reset properly. Before v3.1-rc1 the omapdss driver was managing clocks and resets correctly. However, when omapdss started using runtime PM at v3.1-rc1, the responsibility for the reset moved to HWMOD framework. HWMOD framework does not currently enable all the DSS clocks when resetting the DSS hardware. This hasn't caused any problems so far, but we may just have been lucky. This patch sets HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core in OMAP2xxx HWMOD data, fixing the issue. Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 5 +++++ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 5 +++++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a015c69..8fe373d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -874,12 +874,17 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { }; static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ { .role = "tv_clk", .clk = "dss_54m_fck" }, { .role = "sys_clk", .clk = "dss2_fck" }, }; static struct omap_hwmod omap2420_dss_core_hwmod = { .name = "dss_core", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap2_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ .sdma_reqs = omap2xxx_dss_sdma_chs, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 16743c7..7a5e7f5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -940,12 +940,17 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { }; static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ { .role = "tv_clk", .clk = "dss_54m_fck" }, { .role = "sys_clk", .clk = "dss2_fck" }, }; static struct omap_hwmod omap2430_dss_core_hwmod = { .name = "dss_core", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap2_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ .sdma_reqs = omap2xxx_dss_sdma_chs,