From patchwork Wed Aug 31 13:23:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1116162 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7VDO20G031303 for ; Wed, 31 Aug 2011 13:24:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755841Ab1HaNYB (ORCPT ); Wed, 31 Aug 2011 09:24:01 -0400 Received: from na3sys009aog114.obsmtp.com ([74.125.149.211]:45341 "EHLO na3sys009aog114.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755757Ab1HaNYA (ORCPT ); Wed, 31 Aug 2011 09:24:00 -0400 Received: from mail-wy0-f181.google.com ([74.125.82.181]) (using TLSv1) by na3sys009aob114.postini.com ([74.125.148.12]) with SMTP ID DSNKTl414LAKvDmyS88gm3hlnYY5VOV/8Rdg@postini.com; Wed, 31 Aug 2011 06:23:49 PDT Received: by mail-wy0-f181.google.com with SMTP id 36so543866wyg.26 for ; Wed, 31 Aug 2011 06:23:43 -0700 (PDT) Received: by 10.216.143.211 with SMTP id l61mr431415wej.5.1314797023819; Wed, 31 Aug 2011 06:23:43 -0700 (PDT) Received: from localhost.localdomain (a62-248-128-208.elisa-laajakaista.fi [62.248.128.208]) by mx.google.com with ESMTPS id fm9sm5476855wbb.27.2011.08.31.06.23.42 (version=SSLv3 cipher=OTHER); Wed, 31 Aug 2011 06:23:43 -0700 (PDT) From: Tomi Valkeinen To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org Cc: archit@ti.com, mythripk@ti.com, Tomi Valkeinen Subject: [PATCH 06/12] OMAP: DSS2: HDMI: split hdmi_core_ddc_edid Date: Wed, 31 Aug 2011 16:23:17 +0300 Message-Id: <1314797003-17638-7-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314797003-17638-1-git-send-email-tomi.valkeinen@ti.com> References: <1314797003-17638-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 31 Aug 2011 13:24:03 +0000 (UTC) Split the DDC initialization off from hdmi_core_ddc_edid() into a separate function hdmi_core_ddc_init(). Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/hdmi.c | 67 +++++++++++++++++++++++++++------------- 1 files changed, 45 insertions(+), 22 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index b5aca64..04ce105 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -366,12 +366,8 @@ static void hdmi_phy_off(void) hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); } -static int hdmi_core_ddc_edid(u8 *pedid, int ext) +static int hdmi_core_ddc_init(void) { - u32 i, j; - char checksum = 0; - u32 offset = 0; - /* Turn on CLK for DDC */ REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); @@ -382,32 +378,55 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext) */ usleep_range(800, 1000); - if (!ext) { - /* Clk SCL Devices */ - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); + /* IN_PROG */ + if (REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) { + /* Abort transaction */ + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xf, 3, 0); - /* HDMI_CORE_DDC_STATUS_IN_PROG */ + /* IN_PROG */ if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, - 4, 4, 0) != 0) { - DSSERR("Failed to program DDC\n"); + 4, 4, 0) != 0) { + DSSERR("Timeout aborting DDC transaction\n"); return -ETIMEDOUT; } + } - /* Clear FIFO */ - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); + /* Clk SCL Devices */ + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); - /* HDMI_CORE_DDC_STATUS_IN_PROG */ - if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, - 4, 4, 0) != 0) { - DSSERR("Failed to program DDC\n"); - return -ETIMEDOUT; - } + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { + DSSERR("Timeout starting SCL clock\n"); + return -ETIMEDOUT; + } - } else { - if (ext % 2 != 0) - offset = 0x80; + /* Clear FIFO */ + REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { + DSSERR("Timeout clearing DDC fifo\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_core_ddc_edid(u8 *pedid, int ext) +{ + u32 i, j; + char checksum = 0; + u32 offset = 0; + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { + DSSERR("Timeout waiting DDC to be ready\n"); + return -ETIMEDOUT; } + if (ext % 2 != 0) + offset = 0x80; + /* Load Segment Address Register */ REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); @@ -468,6 +487,10 @@ static int read_edid(u8 *pedid, u16 max_length) int max_ext_blocks = (max_length / 128) - 1; int len; + r = hdmi_core_ddc_init(); + if (r) + return r; + r = hdmi_core_ddc_edid(pedid, 0); if (r) return r;