From patchwork Wed Aug 31 13:42:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 1116552 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7VDhjqj026254 for ; Wed, 31 Aug 2011 13:44:06 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756099Ab1HaNnu (ORCPT ); Wed, 31 Aug 2011 09:43:50 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:34818 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756097Ab1HaNnp (ORCPT ); Wed, 31 Aug 2011 09:43:45 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7VDhG77022653 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 31 Aug 2011 08:43:18 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7VDhFPq023367; Wed, 31 Aug 2011 19:13:15 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Wed, 31 Aug 2011 19:13:16 +0530 Received: from localhost.localdomain ([172.24.190.17]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7VDgvs6011323; Wed, 31 Aug 2011 19:13:15 +0530 (IST) From: Tarun Kanti DebBarma To: CC: , , , Nishanth Menon , Tarun Kanti DebBarma Subject: [PATCH v6 23/25] gpio/omap: enable irq at the end of all configuration in restore Date: Wed, 31 Aug 2011 19:12:39 +0530 Message-ID: <1314798161-19523-24-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1314798161-19523-1-git-send-email-tarun.kanti@ti.com> References: <1314798161-19523-1-git-send-email-tarun.kanti@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 31 Aug 2011 13:44:06 +0000 (UTC) From: Nishanth Menon Setup the interrupt enable registers only after we have configured the required edge and required configurations, not before, to prevent spurious events as part of restore routine. Signed-off-by: Nishanth Menon Signed-off-by: Tarun Kanti DebBarma Reviewed-by: Santosh Shilimkar --- drivers/gpio/gpio-omap.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 67e08e9..db22df8 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -1323,10 +1323,6 @@ void omap2_gpio_resume_after_idle(void) static void omap_gpio_restore_context(struct gpio_bank *bank) { - __raw_writel(bank->context.irqenable1, - bank->base + bank->regs->irqenable); - __raw_writel(bank->context.irqenable2, - bank->base + bank->regs->irqenable2); __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); @@ -1347,6 +1343,10 @@ static void omap_gpio_restore_context(struct gpio_bank *bank) __raw_writel(bank->context.debounce_en, bank->base + bank->regs->debounce_en); } + __raw_writel(bank->context.irqenable1, + bank->base + bank->regs->irqenable); + __raw_writel(bank->context.irqenable2, + bank->base + bank->regs->irqenable2); } #else #define omap_gpio_runtime_suspend NULL