From patchwork Thu Sep 1 17:25:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 1119902 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p81HPcAY030669 for ; Thu, 1 Sep 2011 17:25:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756465Ab1IARZh (ORCPT ); Thu, 1 Sep 2011 13:25:37 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:35551 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756396Ab1IARZg (ORCPT ); Thu, 1 Sep 2011 13:25:36 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p81HPTPY030621 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 1 Sep 2011 12:25:29 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep34.itg.ti.com (8.13.7/8.13.8) with ESMTP id p81HPTHB017244; Thu, 1 Sep 2011 12:25:29 -0500 (CDT) Received: from DFLE70.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p81HPTaq021689; Thu, 1 Sep 2011 12:25:29 -0500 (CDT) Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle70.ent.ti.com (128.247.5.40) with Microsoft SMTP Server id 14.1.323.3; Thu, 1 Sep 2011 12:25:28 -0500 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id p81HPE8a017785; Thu, 1 Sep 2011 12:25:26 -0500 From: Benoit Cousson To: , CC: , , , , Benoit Cousson , Kevin Hilman Subject: [PATCH 2/7] arm/dts: OMAP3: Add mpu and iva nodes Date: Thu, 1 Sep 2011 19:25:07 +0200 Message-ID: <1314897912-18178-3-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1314897912-18178-1-git-send-email-b-cousson@ti.com> References: <1314897912-18178-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 01 Sep 2011 17:25:38 +0000 (UTC) Add nodes for devices used by PM code (mpu, iva). In the case of OMAP3, the dsp was included inside the IVA2.2. Add an empty cpus node as well as recommended in the DT spec. Remove mpu and iva devices init if CONFIG_OF is defined. Signed-off-by: Benoit Cousson Cc: Grant Likely Cc: Kevin Hilman --- arch/arm/boot/dts/omap3.dtsi | 24 ++++++++++++++++++++++++ arch/arm/mach-omap2/pm.c | 6 ++++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 1b27925..5a95a69 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -14,11 +14,35 @@ compatible = "ti,omap3430", "ti,omap3"; /* + * XXX: The cpus node is mandatory, but since the CPUs are as well part + * of the mpu subsystem below, it is not clear where the information + * should be. Maybe here with a phandle inside the mpu? + */ + cpus { + }; + + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + hwmods = "mpu"; + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + iva { + compatible = "ti,iva22", "ti,iva"; + hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64", "ti,c64"; + }; + }; }; /* diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index ba4d187..1fdde69 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -24,6 +24,7 @@ #include "clockdomain.h" #include "pm.h" +#ifndef CONFIG_OF static struct omap_device_pm_latency *pm_lats; static int _init_omap_device(char *name) @@ -53,17 +54,18 @@ static void omap2_init_processor_devices(void) _init_omap_device("iva"); if (cpu_is_omap44xx()) { -#ifndef CONFIG_OF _init_omap_device("mpu"); _init_omap_device("l3_main_1"); _init_omap_device("dsp"); _init_omap_device("iva"); -#endif } else { _init_omap_device("mpu"); _init_omap_device("l3_main"); } } +#else +static void omap2_init_processor_devices(void) {} +#endif /* Types of sleep_switch used in omap_set_pwrdm_state */ #define FORCEWAKEUP_SWITCH 0