From patchwork Sun Sep 4 13:54:18 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1123722 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p84DuBhN027333 for ; Sun, 4 Sep 2011 13:56:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754622Ab1IDN4K (ORCPT ); Sun, 4 Sep 2011 09:56:10 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38046 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754590Ab1IDN4H (ORCPT ); Sun, 4 Sep 2011 09:56:07 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p84DtxXR001906 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 4 Sep 2011 08:56:02 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p84DtxSJ010704; Sun, 4 Sep 2011 19:25:59 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Sun, 4 Sep 2011 19:25:59 +0530 Received: from ula0393909.apr.dhcp.ti.com (ula0393909.apr.dhcp.ti.com [172.24.137.49]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p84DtBN1022822; Sun, 4 Sep 2011 19:25:58 +0530 (IST) From: Santosh Shilimkar To: CC: , , , , Santosh Shilimkar Subject: [PATCH 17/25] OMAP4: PM: CPU1 wakeup workaround from Low power modes Date: Sun, 4 Sep 2011 19:24:18 +0530 Message-ID: <1315144466-9395-18-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1315144466-9395-1-git-send-email-santosh.shilimkar@ti.com> References: <1315144466-9395-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Sun, 04 Sep 2011 13:56:11 +0000 (UTC) The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by: Santosh Shilimkar Cc: Kevin Hilman --- arch/arm/mach-omap2/omap-smp.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index f920abe..4872e04 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -27,6 +27,8 @@ #include #include +#include "clockdomain.h" + /* SCU base address */ static void __iomem *scu_base; @@ -60,6 +62,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { + static struct clockdomain *cpu1_clkdm; + static bool booted; /* * Set synchronisation state between this boot processor * and the secondary one @@ -75,6 +79,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + + if (!cpu1_clkdm) + cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + + /* + * The SGI(Software Generated Interrupts) are not wakeup capable + * from low power states. This is known limitation on OMAP4 and + * needs to be worked around by using software forced clockdomain + * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to + * software force wakeup. The clockdomain is then put back to + * hardware supervised mode. + * More details can be found in OMAP4430 TRM - Version J + * Section : + * 4.3.4.2 Power States of CPU0 and CPU1 + */ + if (booted) { + clkdm_wakeup(cpu1_clkdm); + clkdm_allow_idle(cpu1_clkdm); + } else { + dsb_sev(); + booted = true; + } + gic_raise_softirq(cpumask_of(cpu), 1); /*