From patchwork Thu Sep 8 13:36:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "K, Mythri P" X-Patchwork-Id: 1129892 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p88Digld003719 for ; Thu, 8 Sep 2011 13:44:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932930Ab1IHNoj (ORCPT ); Thu, 8 Sep 2011 09:44:39 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59271 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932907Ab1IHNog (ORCPT ); Thu, 8 Sep 2011 09:44:36 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p88DiWH8013880 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 8 Sep 2011 08:44:34 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88DiVvb003391 for ; Thu, 8 Sep 2011 19:14:31 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Thu, 8 Sep 2011 19:14:31 +0530 Received: from localhost.localdomain (graphicspc.apr.dhcp.ti.com [172.24.136.217]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88DiTJ6027781; Thu, 8 Sep 2011 19:14:31 +0530 (IST) From: To: , CC: Mythri P K Subject: [PATCH 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure Date: Thu, 8 Sep 2011 19:06:20 +0530 Message-ID: <1315488987-4546-4-git-send-email-mythripk@ti.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1315488987-4546-3-git-send-email-mythripk@ti.com> References: <1315488987-4546-1-git-send-email-mythripk@ti.com> <1315488987-4546-2-git-send-email-mythripk@ti.com> <1315488987-4546-3-git-send-email-mythripk@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 08 Sep 2011 13:44:43 +0000 (UTC) From: Mythri P K As hdmi has few additional parameters such as vsync and hsync polarity which is missing in DSS timing structure, define HDMI timings structure for hdmi to use instead of OMAP DSS timing structure. Signed-off-by: Mythri P K --- drivers/video/omap2/dss/hdmi.c | 23 ++++++++++++++++++++--- drivers/video/omap2/dss/hdmi.h | 15 ++++++++++++++- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 47e9f4a..c387bf4 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -534,6 +534,21 @@ static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) return 0; } +static void copy_hdmi_to_dss_timings( + const struct hdmi_video_timings *hdmi_timings, + struct omap_video_timings *timings) +{ + timings->x_res = hdmi_timings->x_res; + timings->y_res = hdmi_timings->y_res; + timings->pixel_clock = hdmi_timings->pixel_clock; + timings->hbp = hdmi_timings->hbp; + timings->hfp = hdmi_timings->hfp; + timings->hsw = hdmi_timings->hsw; + timings->vbp = hdmi_timings->vbp; + timings->vfp = hdmi_timings->vfp; + timings->vsw = hdmi_timings->vsw; +} + static int get_timings_index(void) { int code; @@ -558,7 +573,7 @@ static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) { int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; int timing_vsync = 0, timing_hsync = 0; - struct omap_video_timings temp; + struct hdmi_video_timings temp; struct hdmi_cm cm = {-1}; DSSDBG("hdmi_get_code\n"); @@ -716,7 +731,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp) code = get_timings_index(); - *dp = cea_vesa_timings[code].timings; + copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, dp); + } static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, @@ -1178,7 +1194,8 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi_read_edid(p); } code = get_timings_index(); - dssdev->panel.timings = cea_vesa_timings[code].timings; + copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, + &dssdev->panel.timings); update_hdmi_timings(&hdmi.ip_data.cfg, p, code); phy = p->pixel_clock; diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index d2913f8..02342f6 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -198,9 +198,22 @@ struct hdmi_reg { u16 idx; }; #define REG_GET(base, idx, start, end) \ FLD_GET(hdmi_read_reg(base, idx), start, end) +struct hdmi_video_timings { + u16 x_res; + u16 y_res; + /* Unit: KHz */ + u32 pixel_clock; + u16 hsw; + u16 hfp; + u16 hbp; + u16 vsw; + u16 vfp; + u16 vbp; +}; + /* HDMI timing structure */ struct hdmi_timings { - struct omap_video_timings timings; + struct hdmi_video_timings timings; int vsync_pol; int hsync_pol; };