From patchwork Fri Jun 29 11:53:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruslan Bilovol X-Patchwork-Id: 1131601 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 677CCDFF34 for ; Fri, 29 Jun 2012 11:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753274Ab2F2LxI (ORCPT ); Fri, 29 Jun 2012 07:53:08 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:36421 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752393Ab2F2LxH (ORCPT ); Fri, 29 Jun 2012 07:53:07 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q5TBr4so017630; Fri, 29 Jun 2012 06:53:04 -0500 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q5TBr4jR009756; Fri, 29 Jun 2012 06:53:04 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Fri, 29 Jun 2012 06:53:04 -0500 Received: from localhost (uglx0155540.ucm2.emeaucm.ext.ti.com [10.167.145.75]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q5TBr3LV021008; Fri, 29 Jun 2012 06:53:04 -0500 From: Ruslan Bilovol To: CC: , Subject: [PATCH] OMAP4: Clock: Correct OTG clock to use otg_60m_gfclk. Date: Fri, 29 Jun 2012 14:53:02 +0300 Message-ID: <1340970782-30802-1-git-send-email-ruslan.bilovol@ti.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Wenbiao Wang OTG clock usb_otg_hs_ick used a incorrect parent l3_div_ck. Correct it to use the right colck otg_60m_gfclk as its parent. Signed-off-by: Wenbiao Wang Signed-off-by: Ruslan Bilovol --- arch/arm/mach-omap2/clock44xx_data.c | 15 ++++++++------- 1 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index b825049..fd43214 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -199,12 +199,6 @@ static struct clk tie_low_clock_ck = { .ops = &clkops_null, }; -static struct clk utmi_phy_clkout_ck = { - .name = "utmi_phy_clkout_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - static struct clk xclk60mhsp1_ck = { .name = "xclk60mhsp1_ck", .rate = 60000000, @@ -992,6 +986,13 @@ static struct clk dpll_usb_clkdcoldo_ck = { .recalc = &followparent_recalc, }; +static struct clk utmi_phy_clkout_ck = { + .name = "utmi_phy_clkout_ck", + .ops = &clkops_null, + .parent = &dpll_usb_clkdcoldo_ck, + .recalc = &followparent_recalc, +}; + static const struct clksel dpll_usb_m2_div[] = { { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, { .parent = NULL }, @@ -2685,7 +2686,7 @@ static struct clk usb_otg_hs_ick = { .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, + .parent = &otg_60m_gfclk, .recalc = &followparent_recalc, };