From patchwork Tue Jul 31 00:11:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 1256781 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 62A8F3FCC5 for ; Tue, 31 Jul 2012 00:12:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752546Ab2GaAMi (ORCPT ); Mon, 30 Jul 2012 20:12:38 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:45204 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752308Ab2GaAMi (ORCPT ); Mon, 30 Jul 2012 20:12:38 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6V0Cb5E022481 for ; Mon, 30 Jul 2012 19:12:37 -0500 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6V0CbqO020232 for ; Mon, 30 Jul 2012 19:12:37 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Mon, 30 Jul 2012 19:12:37 -0500 Received: from localhost (dexx0075479.dextra-mty.naucm.ext.ti.com [10.87.226.137]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6V0Cbhe019303; Mon, 30 Jul 2012 19:12:37 -0500 From: Ricardo Neri To: CC: , , , Ricardo Neri Subject: [PATCH v2] OMAPDSS: DISPC: Improve DIGIT channel sync signal selection Date: Mon, 30 Jul 2012 19:11:24 -0500 Message-ID: <1343693484-26133-1-git-send-email-ricardo.neri@ti.com> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org DSS code wrongly assumes that VENC is always available as source for the external sync signal for the display controller DIGIT channel. One cannot blindly rely only on the value of DSS_CONTROL[15] as on certain processors (e.g., OMAP5) reading/writing on that bit may not be valid. If the the sync source is not read correctly, the callers of dss_get_hdmi_venc_clk_source might make wrong assumptions about, for instance, video timings. This patch adds logic to correctly get the sync signal based on the available displays in the DIGIT channel. A kernel BUG is thrown if an invalid source is selected. Signed-off-by: Ricardo Neri --- v2: use BUG_ON() to simplify handling of invalid cases. drivers/video/omap2/dss/dss.c | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 04b4586..2f8e4b6 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -648,9 +648,15 @@ void dss_set_dac_pwrdn_bgz(bool enable) REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ } -void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) +void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) { - REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ + enum omap_display_type dp; + dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); + + BUG_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); + BUG_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); + + REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ } enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) @@ -661,6 +667,9 @@ enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) return DSS_VENC_TV_CLK; + if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) + return DSS_HDMI_M_PCLK; + return REG_GET(DSS_CONTROL, 15, 15); }