From patchwork Thu Aug 23 13:45:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1367251 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E8300DF2AB for ; Thu, 23 Aug 2012 13:45:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934008Ab2HWNps (ORCPT ); Thu, 23 Aug 2012 09:45:48 -0400 Received: from na3sys009aog138.obsmtp.com ([74.125.149.19]:56911 "EHLO na3sys009aog138.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933657Ab2HWNpr (ORCPT ); Thu, 23 Aug 2012 09:45:47 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]) (using TLSv1) by na3sys009aob138.postini.com ([74.125.148.12]) with SMTP ID DSNKUDY0CZn/V9ik3TAe0sbWoshgEyCQLou8@postini.com; Thu, 23 Aug 2012 06:45:46 PDT Received: by lbon3 with SMTP id n3so399316lbo.28 for ; Thu, 23 Aug 2012 06:45:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=vT7ESEnTyb1PoEdGtqXRmxz/PA7pdD01FAWKP8T8eI8=; b=AH+DYHFc4PhWdzZlvSM7sfefGLv0sE0bJKzgV/3WvhHxhEo1bzRvf0Vp17/VC3+4IL h9zs0bImDdYrduu5UzkQ48qvvw1lNq2l7b8E+6n8oeKoFCrML3a4P89d5prY9VEYnZt1 XEVZQyJlruAOAnrNWnDatQ64+Byc7DzdL3JKiRAze3d3B23FzLzMlkEce/PpOjoTtt/r v7oa7KsTSBHUl7lNSHyXYqi4ojdsCDAaq1MYxqRs1JMLTcDOTa6BbP35jiPhWfryS7X7 FUs4ZGsHC3t2udYPHSH3qrQwp1SKv6mm5P053yNJIO8RsvvzmzJMnc8IrCEbDjVilbxe SwAg== Received: by 10.112.26.73 with SMTP id j9mr954540lbg.10.1345729544260; Thu, 23 Aug 2012 06:45:44 -0700 (PDT) Received: from localhost.localdomain (a91-156-160-115.elisa-laajakaista.fi. [91.156.160.115]) by mx.google.com with ESMTPS id fz8sm466816lbb.9.2012.08.23.06.45.41 (version=SSLv3 cipher=OTHER); Thu, 23 Aug 2012 06:45:42 -0700 (PDT) From: Tomi Valkeinen To: archit@ti.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, Tomi Valkeinen , Tony Lindgren Subject: [PATCH 7/8] OMAP: 4430SDP: remove DSI clock config from board file Date: Thu, 23 Aug 2012 16:45:13 +0300 Message-Id: <1345729514-2441-8-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1345729514-2441-1-git-send-email-tomi.valkeinen@ti.com> References: <1345729514-2441-1-git-send-email-tomi.valkeinen@ti.com> X-Gm-Message-State: ALoCoQnW79Lp9MkdlxMoKswx8sOql1/v2907VkVjQVZlYU3Y1MwW/77rkakIZCFScyGdPleGwY5Q Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org DSI clocks are now configured dynamically by the DSI driver, so we can remove the hardcoded clock configuration from the board file. Signed-off-by: Tomi Valkeinen Cc: Tony Lindgren Acked-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 46 ----------------------------------- 1 file changed, 46 deletions(-) diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 852e05c..4352d91 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -621,29 +621,6 @@ static struct omap_dss_device sdp4430_lcd_device = { .phy.dsi = { .module = 0, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD, }; @@ -668,29 +645,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .module = 1, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD2, };