From patchwork Wed Sep 5 08:25:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1406231 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id D368440220 for ; Wed, 5 Sep 2012 08:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758188Ab2IEI04 (ORCPT ); Wed, 5 Sep 2012 04:26:56 -0400 Received: from na3sys009aog112.obsmtp.com ([74.125.149.207]:58817 "EHLO na3sys009aog112.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758190Ab2IEI0y (ORCPT ); Wed, 5 Sep 2012 04:26:54 -0400 Received: from mail-lpp01m010-f46.google.com ([209.85.215.46]) (using TLSv1) by na3sys009aob112.postini.com ([74.125.148.12]) with SMTP ID DSNKUEcMwqOoyCPvNgbWiT+3JmXqhwa5U3ps@postini.com; Wed, 05 Sep 2012 01:26:53 PDT Received: by lagy9 with SMTP id y9so139512lag.19 for ; Wed, 05 Sep 2012 01:26:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=UKbsor1yVouujKyDwTggzjiWQg5llhyr28bdVa0/ntY=; b=VHd+pMG4lZE9cJq927dlfGpBaXj95yuOwrnqzLT/UVkXWgwi4StQvoq+pGeLT4PlVa dIgNXcfMWxhm+Veb/chwJM4uXnPMyUdTnS9FGlTQyC48I9E+DElReWRLoXRjnoWZhH9A JYe6r2IR7kVFC4USSS0ZF8m54s1hlfj/T1gpSLRAms5ElBD9OFj8CNsQrE7oa731Hy3b yAs0aCmIs6zyP/KkxzbvLkNvodnV5GBJyqz7yQRZ11m43cir//hCWTXpTl7cPpH1bwRb v6wKh2xze4rxGyKIlfI6vXuflJhB7//X3rYRF9jxCmovoB37xkJXO/L3UIPLDUNDvaW3 V/2Q== Received: by 10.112.43.137 with SMTP id w9mr7428657lbl.134.1346833601400; Wed, 05 Sep 2012 01:26:41 -0700 (PDT) Received: from localhost.localdomain (a91-156-160-115.elisa-laajakaista.fi. [91.156.160.115]) by mx.google.com with ESMTPS id bc2sm279735lbb.3.2012.09.05.01.26.39 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 01:26:40 -0700 (PDT) From: Tomi Valkeinen To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, archit@ti.com Cc: Tomi Valkeinen Subject: [PATCH 17/17] OMAPDSS: Use WB fifo for GFX overlay Date: Wed, 5 Sep 2012 11:25:55 +0300 Message-Id: <1346833555-31258-18-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346833555-31258-1-git-send-email-tomi.valkeinen@ti.com> References: <1346833555-31258-1-git-send-email-tomi.valkeinen@ti.com> X-Gm-Message-State: ALoCoQkwteIViQ/AtLrfDXEnWuBoBGXAKmx6rNE5yRHMTk4BwYZT+NLd4vgvQ4k0GtE1r8wclNks Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP4's GFX overlay has smaller fifo than the rest of the overlays (including writeback "overlay"). This seems to be the reason for underflows in some more demanding scenarios. We can avoid the problems by using the WB fifo for GFX overlay, and vice versa. WB usage is not supported yet, but when it will, it should perform just fine with smaller fifo as there are no hard realtime constraints with WB. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 27 +++++++++++++++++++++++++++ drivers/video/omap2/dss/dispc.h | 4 ++++ include/video/omapdss.h | 1 + 3 files changed, 32 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index dc0f372..d512c38 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -95,6 +95,9 @@ struct dispc_features { unsigned long (*calc_core_clk) (enum omap_channel channel, u16 width, u16 height, u16 out_width, u16 out_height); u8 num_fifos; + + /* swap GFX & WB fifos */ + bool gfx_fifo_workaround:1; }; #define DISPC_MAX_NR_FIFOS 5 @@ -1088,6 +1091,29 @@ static void dispc_init_fifos(void) */ dispc.fifo_assignment[fifo] = fifo; } + + /* + * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo + * causes problems with certain use cases, like using the tiler in 2D + * mode. The below hack swaps the fifos of GFX and WB planes, thus + * giving GFX plane a larger fifo. WB but should work fine with a + * smaller fifo. + */ + if (dispc.feat->gfx_fifo_workaround) { + u32 v; + + v = dispc_read_reg(DISPC_GLOBAL_BUFFER); + + v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ + v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ + v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ + v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ + + dispc_write_reg(DISPC_GLOBAL_BUFFER, v); + + dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; + dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; + } } static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) @@ -3780,6 +3806,7 @@ static const struct dispc_features omap44xx_dispc_feats __initconst = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .gfx_fifo_workaround = true, }; static int __init dispc_init_features(struct device *dev) diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h index 92d8a9b..42e56cc 100644 --- a/drivers/video/omap2/dss/dispc.h +++ b/drivers/video/omap2/dss/dispc.h @@ -36,6 +36,7 @@ #define DISPC_CONTROL2 0x0238 #define DISPC_CONFIG2 0x0620 #define DISPC_DIVISOR 0x0804 +#define DISPC_GLOBAL_BUFFER 0x0800 #define DISPC_CONTROL3 0x0848 #define DISPC_CONFIG3 0x084C @@ -355,6 +356,8 @@ static inline u16 DISPC_OVL_BASE(enum omap_plane plane) return 0x014C; case OMAP_DSS_VIDEO3: return 0x0300; + case OMAP_DSS_WB: + return 0x0500; default: BUG(); return 0; @@ -517,6 +520,7 @@ static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane) case OMAP_DSS_VIDEO2: return 0x0018; case OMAP_DSS_VIDEO3: + case OMAP_DSS_WB: return 0x0088; default: BUG(); diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 24a7fa1..ac2e4cc 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -73,6 +73,7 @@ enum omap_plane { OMAP_DSS_VIDEO1 = 1, OMAP_DSS_VIDEO2 = 2, OMAP_DSS_VIDEO3 = 3, + OMAP_DSS_WB = 4, }; enum omap_channel {