From patchwork Wed Sep 5 09:01:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 1407001 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 78DF53FC71 for ; Wed, 5 Sep 2012 09:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758163Ab2IEJCT (ORCPT ); Wed, 5 Sep 2012 05:02:19 -0400 Received: from na3sys009aog131.obsmtp.com ([74.125.149.247]:54066 "EHLO na3sys009aog131.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932651Ab2IEJBx (ORCPT ); Wed, 5 Sep 2012 05:01:53 -0400 Received: from mail-yw0-f52.google.com ([209.85.213.52]) (using TLSv1) by na3sys009aob131.postini.com ([74.125.148.12]) with SMTP ID DSNKUEcU+wWKlTCb0+02fITdGlyYYDqorh9k@postini.com; Wed, 05 Sep 2012 02:01:53 PDT Received: by yhpp61 with SMTP id p61so36874yhp.11 for ; Wed, 05 Sep 2012 02:01:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=4sK+1qfnbX8SzknBvuA2qz5c7PUGqaQGrT0PsWsyv9k=; b=QagPeTcP/Tbj2D2GaA9pRRYIAriNTaYuHzAca5ECVsKhsDxw1Y4oROjC8dXIggXW6t 6zTc/hfxnZN0wYRi+spY4vEdCQNaLWaH1QSfyACKahYV7mq4663saZopsQacczHwuSoV H3RUbamTDEJV8TDO4HLkHoxNbdaPDcnKEprIne/FVBMvIoK7Y0l1Zsf3OlwK9b+ovTUx BU7fro1MyPko0GDzRs+0F7+Xf6fXywvEZ88PWRVVZCpWlktQUdMmb46wGl++IAXhjQXV 5WsHsEDsvbXusPWQskEzfRWuybba5p2k8enpt6ufZ7asVZ2YB01WWn4c5Ite8JdKqem7 JHmw== Received: by 10.236.191.233 with SMTP id g69mr21765186yhn.113.1346835707046; Wed, 05 Sep 2012 02:01:47 -0700 (PDT) Received: from barack.emea.dhcp.ti.com (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id h8sm1047114ank.9.2012.09.05.02.01.44 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 02:01:45 -0700 (PDT) From: Peter Ujfalusi To: Linus Walleij , Tony Lindgren Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH 2/2] pinctrl: pinctrl-single: Add pinctrl-single, bits type of mux Date: Wed, 5 Sep 2012 12:01:58 +0300 Message-Id: <1346835718-21325-3-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1346835718-21325-1-git-send-email-peter.ujfalusi@ti.com> References: <1346835718-21325-1-git-send-email-peter.ujfalusi@ti.com> X-Gm-Message-State: ALoCoQnzud24DfC6ROir49OgltKXge0RCvsj0WbQZx+iLsS4Cey0FNk/lSJEDCtTNiMHLlL0yF36 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org With pinctrl-single,bits it is possible to update just part of the register within the pinctrl-single,function-mask area. This is useful when one register configures mmore than one pin's mux. pinctrl-single,bits takes three parameters: Signed-off-by: Peter Ujfalusi --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 9 +++++ drivers/pinctrl/pinctrl-single.c | 42 ++++++++++++++++------ 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 5187f0d..287801d 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -31,6 +31,15 @@ device pinctrl register, and 0x118 contains the desired value of the pinctrl register. See the device example and static board pins example below for more information. +In case when one register changes more than one pin's mux the +pinctrl-single,bits can be used which takes three parameters: + + pinctrl-single,bits = <0xdc 0x18, 0xff>; + +Where 0xdc is the offset from the pinctrl register base address for the +device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to +be used when applying this change to the register. + Example: /* SoC common file */ diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 3508631..aec338e 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -26,7 +26,8 @@ #include "core.h" #define DRIVER_NAME "pinctrl-single" -#define PCS_MUX_NAME "pinctrl-single,pins" +#define PCS_MUX_PINS_NAME "pinctrl-single,pins" +#define PCS_MUX_BITS_NAME "pinctrl-single,bits" #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) #define PCS_OFF_DISABLED ~0U @@ -54,6 +55,7 @@ struct pcs_pingroup { struct pcs_func_vals { void __iomem *reg; unsigned val; + unsigned mask; }; /** @@ -332,12 +334,17 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, for (i = 0; i < func->nvals; i++) { struct pcs_func_vals *vals; - unsigned val; + unsigned val, mask; vals = &func->vals[i]; val = pcs->read(vals->reg); - val &= ~pcs->fmask; - val |= (vals->val & pcs->fmask); + if (!vals->mask) + mask = pcs->fmask; + else + mask = pcs->fmask & vals->mask; + + val &= ~mask; + val |= (vals->val & mask); pcs->write(val, vals->reg); } @@ -657,18 +664,29 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, { struct pcs_func_vals *vals; const __be32 *mux; - int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; + int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; struct pcs_function *function; - mux = of_get_property(np, PCS_MUX_NAME, &size); - if ((!mux) || (size < sizeof(*mux) * 2)) { - dev_err(pcs->dev, "bad data for mux %s\n", - np->name); + mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); + if (mux) { + params = 2; + } else { + mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); + if (!mux) { + dev_err(pcs->dev, "no valid property for %s\n", + np->name); + return -EINVAL; + } + params = 3; + } + + if (size < (sizeof(*mux) * params)) { + dev_err(pcs->dev, "bad data for %s\n", np->name); return -EINVAL; } size /= sizeof(*mux); /* Number of elements in array */ - rows = size / 2; /* Each row is a key value pair */ + rows = size / params; /* Each row is a key value pair */ vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); if (!vals) @@ -686,6 +704,10 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, val = be32_to_cpup(mux + index++); vals[found].reg = pcs->base + offset; vals[found].val = val; + if (params == 3) { + val = be32_to_cpup(mux + index++); + vals[found].mask = val; + } pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) {