From patchwork Wed Sep 5 19:04:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1410191 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 521943FC71 for ; Wed, 5 Sep 2012 19:04:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759197Ab2IETEx (ORCPT ); Wed, 5 Sep 2012 15:04:53 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:32783 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759005Ab2IETEw (ORCPT ); Wed, 5 Sep 2012 15:04:52 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q85J4l73008870; Wed, 5 Sep 2012 14:04:47 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q85J4l2e009491; Wed, 5 Sep 2012 14:04:47 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Wed, 5 Sep 2012 14:04:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id q85J4l7H011513; Wed, 5 Sep 2012 14:04:47 -0500 Received: from localhost (ula0741266.am.dhcp.ti.com [192.157.144.139]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q85J4kr07279; Wed, 5 Sep 2012 14:04:46 -0500 (CDT) From: Jon Hunter To: Tony Lindgren , Kevin Hilman , Paul Walmsley CC: linux-omap , linux-arm , Jon Hunter Subject: [PATCH 07/10] ARM: OMAP: Clean-up dmtimer reset code Date: Wed, 5 Sep 2012 14:04:29 -0500 Message-ID: <1346871872-24413-8-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1346871872-24413-1-git-send-email-jon-hunter@ti.com> References: <1346871872-24413-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Only OMAP1 devices use the omap_dm_timer_reset() and so require the omap_dm_timer_wait_for_reset() and __omap_dm_timer_reset() functions. Therefore combine these into a single function called omap_dm_timer_reset() and simplify the code. Please note that for OMAP1 devices, the TIOCP_CFG register does not have the clock-activity field and so when we reset the timer for an OMAP1 device we only need to configure the idle-mode field in the TIOCP_CFG register. Signed-off-by: Jon Hunter --- arch/arm/plat-omap/dmtimer.c | 40 +++++++++++++++++------------ arch/arm/plat-omap/include/plat/dmtimer.h | 19 -------------- 2 files changed, 24 insertions(+), 35 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 623c1f3..1eb7353 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -43,6 +43,7 @@ #include #include +#include #include @@ -103,32 +104,34 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer) timer->context.tclr); } -static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) +static int omap_dm_timer_reset(struct omap_dm_timer *timer) { - int c; + u32 l, timeout = 0; if (!timer->sys_stat) - return; + return -EINVAL; + + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); - c = 0; while (!(__raw_readl(timer->sys_stat) & 1)) { - c++; - if (c > 100000) { - printk(KERN_ERR "Timer failed to reset\n"); - return; + if (timeout++ > 100000) { + dev_err(&timer->pdev->dev, "Timer failed to reset\n"); + return -ETIMEDOUT; } } -} -static void omap_dm_timer_reset(struct omap_dm_timer *timer) -{ - omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); - omap_dm_timer_wait_for_reset(timer); - __omap_dm_timer_reset(timer, 0, 0); + /* Configure timer for smart-idle mode */ + l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); + l |= __ffs(HWMOD_IDLEMODE_SMART) << SYSC_TYPE1_SIDLEMODE_SHIFT; + __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); + + return 0; } int omap_dm_timer_prepare(struct omap_dm_timer *timer) { + int rc; + /* * FIXME: OMAP1 devices do not use the clock framework for dmtimers so * do not call clk_get() for these devices. @@ -144,8 +147,13 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) omap_dm_timer_enable(timer); - if (timer->capability & OMAP_TIMER_NEEDS_RESET) - omap_dm_timer_reset(timer); + if (timer->capability & OMAP_TIMER_NEEDS_RESET) { + rc = omap_dm_timer_reset(timer); + if (rc) { + omap_dm_timer_disable(timer); + return rc; + } + } __omap_dm_timer_enable_posted(timer); omap_dm_timer_disable(timer); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index fa9d04b..6488a19 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -331,25 +331,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) } } -/* Assumes the source clock has been set by caller */ -static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, - int autoidle, int wakeup) -{ - u32 l; - - l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); - l |= 0x02 << 3; /* Set to smart-idle mode */ - l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ - - if (autoidle) - l |= 0x1 << 0; - - if (wakeup) - l |= 1 << 2; - - __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); -} - static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer) { if (timer->posted)