From patchwork Fri Sep 7 09:09:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1420871 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id AD5CCDF283 for ; Fri, 7 Sep 2012 09:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758199Ab2IGJJm (ORCPT ); Fri, 7 Sep 2012 05:09:42 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57232 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753066Ab2IGJJl (ORCPT ); Fri, 7 Sep 2012 05:09:41 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8799RjY013246; Fri, 7 Sep 2012 04:09:28 -0500 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8799OSc001181; Fri, 7 Sep 2012 14:39:25 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Fri, 7 Sep 2012 14:39:24 +0530 Received: from a0393678lt.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8799IAN021390; Fri, 7 Sep 2012 14:39:19 +0530 From: Kishon Vijay Abraham I To: , , , , , , , , , CC: Kishon Vijay Abraham I Subject: [PATCH v2] arm: omap: hwmod: make *phy_48m* as the main_clk of ocp2scp Date: Fri, 7 Sep 2012 14:39:15 +0530 Message-ID: <1347008955-21310-1-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Made *ocp2scp_usb_phy_phy_48m* as the main_clk for ocp2scp. Since this ocp2scp module does not have any fck but does have a single opt_clock, it is added as the main_clk for ocp2scp. Also removed phy_48m as the optional clock since it is now made as the main clock. By this the driver need not enable/disable phy_48m clk separately and runtime_get/runtime_put will take care of that. Cc: Benoît Cousson Reviewed-by: Felipe Balbi Signed-off-by: Kishon Vijay Abraham I --- Changes for v1: Amend the comment section with benefit for the driver because of this patch. arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 242aee4..e8e5405 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2503,14 +2503,11 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { }; /* ocp2scp_usb_phy */ -static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { - { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, -}; - static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", + .main_clk = "ocp2scp_usb_phy_phy_48m", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, @@ -2518,8 +2515,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .opt_clks = ocp2scp_usb_phy_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), }; /*