From patchwork Wed Sep 12 19:45:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omar Ramirez Luna X-Patchwork-Id: 1446271 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id D831C3FE79 for ; Wed, 12 Sep 2012 19:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752680Ab2ILTsG (ORCPT ); Wed, 12 Sep 2012 15:48:06 -0400 Received: from mail-oa0-f46.google.com ([209.85.219.46]:57246 "EHLO mail-oa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752209Ab2ILTqH (ORCPT ); Wed, 12 Sep 2012 15:46:07 -0400 Received: by mail-oa0-f46.google.com with SMTP id o6so1280290oag.19 for ; Wed, 12 Sep 2012 12:46:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Qu67A/yagFI5h5DWfLmIb9eq1bVbvRKfw41TU0TX8+I=; b=l7WCaxDOVytc2qQjxdbzRECLU89npBPr0CXLyEhOBAPQhZWYmy2cG7gX79Y9xH/oe+ 6/crK3tkKMTMzj8tM7exr9Uvr+bDRMRUM2k5QrSuiPFp3BlTh7FgWuh2Y/a4N0R/82SR LgPCVXDxAry+veLkfUbszpHVp6yqcDJ9WV+0MbHDK9WrA/1gmsMA5IFB7rz600efKSRF WihE4uZ61DgfRJoIqapN6+s0b4GcIT7Dbwmr0POpBdO/rQ8dZmr5KBDFlkIiVqO/2YLw ncjI+59miAagfafTJ8AyOolwgKEOIYCExWSS0hsn/6DAxzXOeEPs7fc1zeeWjuVNibxv YcTg== Received: by 10.60.22.196 with SMTP id g4mr24690787oef.95.1347479166785; Wed, 12 Sep 2012 12:46:06 -0700 (PDT) Received: from uda0273944.am.dhcp.ti.com (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id a6sm17041227oeh.1.2012.09.12.12.46.05 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Sep 2012 12:46:06 -0700 (PDT) From: Omar Ramirez Luna To: Tony Lindgren , Benoit Cousson , Ohad Ben-Cohen , Joerg Roedel Cc: Russell King , Omar Ramirez Luna , Rajendra Nayak , Peter Ujfalusi , Laurent Pinchart , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Subject: [PATCH v2 3/9] ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp Date: Wed, 12 Sep 2012 14:45:46 -0500 Message-Id: <1347479152-588-4-git-send-email-omar.luna@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347479152-588-1-git-send-email-omar.luna@linaro.org> References: <1347479152-588-1-git-send-email-omar.luna@linaro.org> X-Gm-Message-State: ALoCoQl471XO+LHCxhquWddC7H0PITDQBblC1iIC+CJm/QAyi+aVd6yZOawUJTeDgl5uHAYEfBX7 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add mmu hwmod data for ipu and dsp. Cc: Benoit Cousson Signed-off-by: Omar Ramirez Luna Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 136 +++++++++++++++++++++++++++- 1 file changed, 134 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 242aee4..c2cf25a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" @@ -612,7 +613,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { { .name = "dsp", .rst_shift = 0 }, - { .name = "mmu_cache", .rst_shift = 1 }, }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1632,7 +1632,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, { .name = "cpu1", .rst_shift = 1 }, - { .name = "mmu_cache", .rst_shift = 2 }, }; static struct omap_hwmod omap44xx_ipu_hwmod = { @@ -2439,6 +2438,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig mmu_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &mmu_sysc, +}; + +/* mmu ipu */ + +static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { + { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { + { + .pa_start = 0x55082000, + .pa_end = 0x550820ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3_main_2 -> mmu_ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_mmu_ipu_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_mmu_ipu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { + .name = "mmu_ipu", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "ducati_clkdm", + .mpu_irqs = omap44xx_mmu_ipu_irqs, + .rst_lines = omap44xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), + .main_clk = "ducati_clk_mux_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_ipu_dev_attr, +}; + +/* mmu dsp */ + +static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { + { .irq = 28 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { + { + .pa_start = 0x4a066000, + .pa_end = 0x4a0660ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mmu_dsp_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmu_dsp_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { + .name = "mmu_dsp", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "tesla_clkdm", + .mpu_irqs = omap44xx_mmu_dsp_irqs, + .rst_lines = omap44xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), + .main_clk = "dpll_iva_m4x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_dsp_dev_attr, +}; + +/* * 'mpu' class * mpu sub-system */ @@ -6092,6 +6222,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l3_main_2__mmu_ipu, + &omap44xx_l4_cfg__mmu_dsp, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_mpu_private__prcm_mpu,