From patchwork Thu Sep 13 10:20:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1451241 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id A79ADDF28C for ; Thu, 13 Sep 2012 10:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757157Ab2IMKV2 (ORCPT ); Thu, 13 Sep 2012 06:21:28 -0400 Received: from service87.mimecast.com ([91.220.42.44]:47771 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755809Ab2IMKVJ (ORCPT ); Thu, 13 Sep 2012 06:21:09 -0400 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 13 Sep 2012 11:21:08 +0100 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 13 Sep 2012 11:21:05 +0100 From: Lorenzo Pieralisi To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Russell King , Nicolas Pitre , Colin Cross , Daniel Lezcano , Amit Kucheria , Dave Martin , Wenzeng Chen Subject: [RFC PATCH 3/6] ARM: mm: add v7 dcache level API Date: Thu, 13 Sep 2012 11:20:48 +0100 Message-Id: <1347531651-28218-4-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 13 Sep 2012 10:21:05.0784 (UTC) FILETIME=[7BDEDF80:01CD9199] X-MC-Unique: 112091311210804001 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Santosh Shilimkar On ARMv7 based SOC with an integrated L2 cache, there is a need to have a flush API to operate on each cache level. In few low power modes, L2 cache is retained whereas L1 is lost. The current v7_flush_dcache_all(), flushes all the levels and it would be quite expensive in cases where only one of the level needs to be flushed. So this patch introduces v7_flush_dcache_level() API which takes a parameter (cache level), and flush only that level. This API is useful for the power management code where depending on CPU and CPU cluster low power state, a specific cache level can be cleaned instead of cleaning all the cache levels with existing flush_dcache_all(). Signed-off-by: Santosh Shilimkar Signed-off-by: Lorenzo Pieralisi --- arch/arm/mm/cache-v7.S | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 74aec79..d0fbe5c 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -51,6 +51,26 @@ ENTRY(v7_flush_dcache_louis) b __flush_level ENDPROC(v7_flush_dcache_louis) + /* + * v7_flush_dcache_level(level) + * + * Flush the D-cache the specified level passed as input parameter. + * + * r0 - cache level + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + */ + +ENTRY(v7_flush_dcache_level) + dmb @ ensure ordering with previous memory accesses + sub r10, r0, #1 + mov r10, r10, lsl #1 + movs r3, r0, lsl #1 @ level * 2 + mrc p15, 1, r0, c0, c0, 1 @ read clidr + moveq pc, lr @ return if level == 0 + b __flush_level +ENDPROC(v7_flush_dcache_level) + /* * v7_flush_dcache_all() *