From patchwork Thu Sep 13 10:20:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1451211 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 901E8DF28C for ; Thu, 13 Sep 2012 10:21:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757315Ab2IMKVY (ORCPT ); Thu, 13 Sep 2012 06:21:24 -0400 Received: from service87.mimecast.com ([91.220.42.44]:47852 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756340Ab2IMKVK (ORCPT ); Thu, 13 Sep 2012 06:21:10 -0400 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 13 Sep 2012 11:21:09 +0100 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 13 Sep 2012 11:21:07 +0100 From: Lorenzo Pieralisi To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Russell King , Nicolas Pitre , Colin Cross , Santosh Shilimkar , Daniel Lezcano , Amit Kucheria , Dave Martin , Wenzeng Chen Subject: [RFC PATCH 5/6] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Date: Thu, 13 Sep 2012 11:20:50 +0100 Message-Id: <1347531651-28218-6-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 13 Sep 2012 10:21:07.0362 (UTC) FILETIME=[7CCFA820:01CD9199] X-MC-Unique: 112091311210903901 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org When a CPU is hotplugged out caches that reside in its power domain lose their contents and so must be cleaned to the next memory level. Currently, __cpu_disable calls flush_cache_all() that for new generation processor like A15/A7 ends up cleaning and invalidating all cache levels up to Level of Coherency, which includes the unified L2. This ends up being a waste of cycles since the L2 cache contents are not lost on power down. This patch updates __cpu_disable to use the new LoUIS API cache operations. Reviewed-by: Santosh Shilimkar Signed-off-by: Lorenzo Pieralisi --- arch/arm/kernel/smp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index d3eb222..f44e9cd 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -136,8 +136,11 @@ int __cpu_disable(void) /* * Flush user cache and TLB mappings, and then remove this CPU * from the vm mask set of all processes. + * + * Caches are flushed to the Level of Unification Inner Shareable + * to write-back dirty lines to unified caches shared by all CPUs. */ - flush_cache_all(); + flush_cache_louis(); local_flush_tlb_all(); clear_tasks_mm_cpumask(cpu);