From patchwork Tue Sep 18 08:52:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 1471291 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id A5B64400EC for ; Tue, 18 Sep 2012 08:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757693Ab2IRIwh (ORCPT ); Tue, 18 Sep 2012 04:52:37 -0400 Received: from mail-wg0-f42.google.com ([74.125.82.42]:45346 "EHLO mail-wg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756864Ab2IRIwc (ORCPT ); Tue, 18 Sep 2012 04:52:32 -0400 Received: by wgbfm10 with SMTP id fm10so2728778wgb.1 for ; Tue, 18 Sep 2012 01:52:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=1+Fdb/g4m7AOEiMFjOe95Jmy3PVX8+itNpqwTtuCphs=; b=UmINNLBONNB8idLedU/P1HUi+uZ0AsiWVyniPYmb2qxXqM2AQL+Jkh1n/5SWAmEqy8 d5yUoXF80JscVsYhlL7IVbJr/XbhB0CmjGesJj6vAyC4D5w5+SlHbD4l/5j7gDxLWjlG hGc1csZCN2hfKGv3K15tDpEuW4lwFQsTOIQ8EtYBDTP1f8yDwkxRQ/p3fYuNCQN4d+Gq r4gtVZgAJAwnD8HzKWcv+2MunCuWFjJQq2FRxt6VlDrRmZvFLcuYtp5KcgSU/dKGuKHY 0zwlpMKvkObdW/1Fp/Cq3ULjvY4d7fqAZMRDlw++SXzZ/t5INyErotymXSmKJRE5/c14 qSiA== Received: by 10.216.131.13 with SMTP id l13mr7591805wei.195.1347958350298; Tue, 18 Sep 2012 01:52:30 -0700 (PDT) Received: from localhost.localdomain (179.59-66-87.adsl-dyn.isp.belgacom.be. [87.66.59.179]) by mx.google.com with ESMTPS id ct3sm21831091wib.5.2012.09.18.01.52.29 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Sep 2012 01:52:29 -0700 (PDT) From: Jean Pihet To: linux-omap@vger.kernel.org, paul@pwsan.com, linux-arm-kernel@lists.infradead.org, khilman@ti.com Cc: Jean Pihet Subject: [PATCH 5/8] ARM: OMAP3: update cpuidle latency and threshold figures Date: Tue, 18 Sep 2012 10:52:09 +0200 Message-Id: <1347958332-2205-6-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1347958332-2205-1-git-send-email-j-pihet@ti.com> References: <1347958332-2205-1-git-send-email-j-pihet@ti.com> X-Gm-Message-State: ALoCoQmzMxihmzJnP7ZvqJ+UQk2KtS0Ebi7OFYevV+yIDu1Ll7DOTKjyinS1p+WJEJfU3Icieswb Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Update the data from the measurements performed at HW and SW levels. Cf. http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement for a detailed explanation on where are the numbers coming from. ToDo: - Measure the wake-up latencies for all power domains for OMAP3 - Correct some numbers when sys_clkreq and sys_offmode are supported Signed-off-by: Jean Pihet Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 54 ++++++++++++++++++++++++++---------- 1 files changed, 39 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index ca6cb71..c086374 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -280,63 +280,87 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); * * - target_residency: required amount of time in the C state * to break even on energy cost + * + * The MPU latency and threshold values for the C-states are the worst case + * values from the HW and SW, as described in details at + * http://www.omappedia.org/wiki/Power_Management_Device_Latencies_Measurement#cpuidle_results + * + * Measurements conditions and remarks: + * . the measurements have been performed at OPP50 + * . the sys_offmode signal is not supported and so not used for the + * measurements. Instead the latency and threshold values for C9 are + * corrected with the value for Triton 2, which is 11.5ms + * . the sys_clkreq signal is not used and so a correction is needed - TBD + * . the sys_clkoff signal is supported, this value need to be corrected with + * the correct value of SYSCLK on/off timings (1ms for sysclk on, 2.5ms + * for sysclk off) + * . the setup time of DPLLs is included in the measured values. However + * this is only valid for DPLLs that are enabled to auto-idle at + * measurement time. There currently is no provision for the dynamic + * nature of the auto-idle setting + * . in order to force the cpuidle algorithm to chose the power efficient + * C-states (C1, C3, C5, C7) in preference, the other C-states have a + * threshold value equal to the next power efficient C-state + * + * The latency and threshold values can be overriden by data from the board + * files, using omap3_pm_init_cpuidle. */ struct cpuidle_driver omap3_idle_driver = { .name = "omap3_idle", .owner = THIS_MODULE, .states = { { - .enter = omap3_enter_idle_bm, - .exit_latency = 2 + 2, - .target_residency = 5, + .enter = omap3_enter_idle, + .exit_latency = 73 + 78, + .target_residency = 152, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C1", .desc = "MPU ON + CORE ON", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 10 + 10, - .target_residency = 30, + .exit_latency = 165 + 88, + .target_residency = 345, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C2", .desc = "MPU ON + CORE ON", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 50 + 50, - .target_residency = 300, + .exit_latency = 163 + 182, + .target_residency = 345, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C3", .desc = "MPU RET + CORE ON", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 1500 + 1800, - .target_residency = 4000, + .exit_latency = 2852 + 605, + .target_residency = 150000, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C4", .desc = "MPU OFF + CORE ON", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 2500 + 7500, - .target_residency = 12000, + .exit_latency = 800 + 366, + .target_residency = 2120, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C5", .desc = "MPU RET + CORE RET", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 3000 + 8500, - .target_residency = 15000, + .exit_latency = 4080 + 801, + .target_residency = 215000, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C6", .desc = "MPU OFF + CORE RET", }, { .enter = omap3_enter_idle_bm, - .exit_latency = 10000 + 30000, - .target_residency = 30000, + .exit_latency = 4300 + 13000, + .target_residency = 215000, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "C7", .desc = "MPU OFF + CORE OFF",