From patchwork Tue Sep 18 16:35:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1473581 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 2504F3FCFC for ; Tue, 18 Sep 2012 16:36:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751742Ab2IRQgI (ORCPT ); Tue, 18 Sep 2012 12:36:08 -0400 Received: from service87.mimecast.com ([91.220.42.44]:40698 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751703Ab2IRQgD (ORCPT ); Tue, 18 Sep 2012 12:36:03 -0400 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 18 Sep 2012 17:36:01 +0100 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 18 Sep 2012 17:36:00 +0100 From: Lorenzo Pieralisi To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Russell King , Nicolas Pitre , Colin Cross , Daniel Lezcano , Amit Kucheria , Dave Martin , Wenzeng Chen Subject: [RFC PATCH v2 5/5] ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API Date: Tue, 18 Sep 2012 17:35:35 +0100 Message-Id: <1347986135-17979-6-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347986135-17979-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1347986135-17979-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 18 Sep 2012 16:36:00.0468 (UTC) FILETIME=[AFD00140:01CD95BB] X-MC-Unique: 112091817360114901 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Santosh Shilimkar The ARMv7 processor setup function __v7_setup() cleans and invalidates the CPU cache before enabling MMU to start the CPU with a clean CPU local cache. But on ARMv7 architectures like Cortex-[A15/A8], this code will end up flushing the L2 caches(up to level of Coherency) which is undesirable and expensive. The setup functions are used in the CPU hotplug scenario too and hence flushing all cache levels should be avoided. This patch replaces the cache flushing call with the newly introduced v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and invalidated when a processors executes __v7_setup which is the expected behavior. For processors like A9 and A5 where the L2 cache is an outer one the behavior should be unchanged. Signed-off-by: Santosh Shilimkar Signed-off-by: Lorenzo Pieralisi Reviewed-by: Nicolas Pitre --- arch/arm/mm/proc-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66..846d279 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -172,7 +172,7 @@ __v7_ca15mp_setup: __v7_setup: adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} - bl v7_flush_dcache_all + bl v7_flush_dcache_louis ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register