From patchwork Mon Oct 22 16:15:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 1626911 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id A75BF4020E for ; Mon, 22 Oct 2012 16:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755613Ab2JVQPi (ORCPT ); Mon, 22 Oct 2012 12:15:38 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:46927 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753240Ab2JVQPi (ORCPT ); Mon, 22 Oct 2012 12:15:38 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9MGFYN1007444; Mon, 22 Oct 2012 11:15:34 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9MGFYaT002469; Mon, 22 Oct 2012 11:15:34 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Mon, 22 Oct 2012 11:15:34 -0500 Received: from localhost.localdomain (h68-5.vpn.ti.com [172.24.68.5]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9MGFWUV014002; Mon, 22 Oct 2012 11:15:32 -0500 From: Tero Kristo To: CC: , Paul Walmsley , Benoit Cousson , Venkatraman S Subject: [RFC] ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod Date: Mon, 22 Oct 2012 19:15:32 +0300 Message-ID: <1350922532-26338-1-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org When waking up from off-mode, some IP blocks are reset automatically by hardware. For this reason, software must wait until the reset has completed before attempting to access the IP block. This patch fixes for example the bug introduced by commit 6c31b2150ff96755d24e0ab6d6fea08a7bf5c44c ("mmc: omap_hsmmc: remove access to SYSCONFIG register"), in which the MMC IP block is reset during off-mode entry, but the code expects the module to be already available during the execution of context restore. Signed-off-by: Tero Kristo Cc: Paul Walmsley Cc: Benoit Cousson Cc: Venkatraman S Tested-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index b969ab1..523729b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1278,6 +1278,7 @@ static void _enable_sysc(struct omap_hwmod *oh) u8 idlemode, sf; u32 v; bool clkdm_act; + int c; if (!oh->class->sysc) return; @@ -1338,6 +1339,27 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_module_autoidle(oh, idlemode, &v); _write_sysconfig(v, oh); } + + /* + * Wait until reset has completed, this is needed as the IP + * block is reset automatically by hardware in some cases + * (off-mode for example), and the drivers require the + * IP to be ready when they access it + */ + if (sf & SYSS_HAS_RESET_STATUS) + omap_test_timeout((omap_hwmod_read(oh, + oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + + if (sf & SYSC_HAS_RESET_STATUS) { + u32 softrst_mask = + (0x1 << oh->class->sysc->sysc_fields->srst_shift); + omap_test_timeout(!(omap_hwmod_read(oh, + oh->class->sysc->sysc_offs) + & softrst_mask), + MAX_MODULE_SOFTRESET_WAIT, c); + } } /**