From patchwork Fri Nov 2 12:32:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Bedia X-Patchwork-Id: 1688281 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 29C8F3FD4E for ; Fri, 2 Nov 2012 12:34:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755217Ab2KBMe1 (ORCPT ); Fri, 2 Nov 2012 08:34:27 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:39675 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760789Ab2KBMe0 (ORCPT ); Fri, 2 Nov 2012 08:34:26 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA2CYEfj021961; Fri, 2 Nov 2012 07:34:14 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA2CYAsE022142; Fri, 2 Nov 2012 18:04:13 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Fri, 2 Nov 2012 18:04:11 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA2CY79H022950; Fri, 2 Nov 2012 18:04:11 +0530 From: Vaibhav Bedia To: , CC: , , , , Vaibhav Bedia Subject: [PATCH 07/15] ARM: OMAP2+: hwmod: Update the hwmod data for TPTCs in AM33XX Date: Fri, 2 Nov 2012 18:02:38 +0530 Message-ID: <1351859566-24818-8-git-send-email-vaibhav.bedia@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com> References: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Update the TPTC hwmod entry to reflect the fact that the idle and standby transitions are s/w controlled. Signed-off-by: Vaibhav Bedia Acked-by: Vaibhav Hiremath --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index ec3fbb2..7772c29 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -1827,6 +1827,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = { .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", .mpu_irqs = am33xx_tptc0_irqs, + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .main_clk = "l3_gclk", .prcm = { .omap4 = {