From patchwork Mon Dec 10 07:09:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1855401 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E1576DFB79 for ; Mon, 10 Dec 2012 07:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752203Ab2LJHJa (ORCPT ); Mon, 10 Dec 2012 02:09:30 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:54892 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752053Ab2LJHJ3 (ORCPT ); Mon, 10 Dec 2012 02:09:29 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qBA79OQ4012566; Mon, 10 Dec 2012 01:09:25 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBA79N7h004475; Mon, 10 Dec 2012 12:39:23 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Mon, 10 Dec 2012 12:39:23 +0530 Received: from a0131933lt.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBA79KlK030499; Mon, 10 Dec 2012 12:39:23 +0530 From: Lokesh Vutla To: CC: , , , , , Nishanth Menon Subject: [PATCH 2/9] memory: emif: setup LP settings on freq update Date: Mon, 10 Dec 2012 12:39:11 +0530 Message-ID: <1355123358-5273-3-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355123358-5273-1-git-send-email-lokeshvutla@ti.com> References: <1355123358-5273-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Nishanth Menon Program the power management shadow register on freq update else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: Nishanth Menon --- drivers/memory/emif.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c index 8589aba..69a480d 100644 --- a/drivers/memory/emif.c +++ b/drivers/memory/emif.c @@ -815,6 +815,11 @@ static void setup_registers(struct emif_data *emif, struct emif_regs *regs) writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); + if (emif->lpmode != EMIF_LP_MODE_DISABLE) { + writel(regs->pwr_mgmt_ctrl_shdw, + base + EMIF_POWER_MANAGEMENT_CTRL_SHDW); + } + /* Settings specific for EMIF4D5 */ if (emif->plat_data->ip_rev != EMIF_4D5) return;