From patchwork Mon Mar 4 11:35:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 2212081 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 9A54EDF2F2 for ; Mon, 4 Mar 2013 11:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757159Ab3CDLgc (ORCPT ); Mon, 4 Mar 2013 06:36:32 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:42328 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757156Ab3CDLgb (ORCPT ); Mon, 4 Mar 2013 06:36:31 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r24Ba5aM017028; Mon, 4 Mar 2013 05:36:06 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r24Ba22N004766; Mon, 4 Mar 2013 17:06:05 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Mon, 4 Mar 2013 17:06:02 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r24BZwRU026037; Mon, 4 Mar 2013 17:06:01 +0530 From: To: CC: , , , , , Vaibhav Hiremath Subject: [RFC PATCH 1/3] ARM: AM33XX: clock: Add debugSS clock nodes to clock tree Date: Mon, 4 Mar 2013 17:05:55 +0530 Message-ID: <1362396957-30113-2-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Vaibhav Hiremath Represent debugSS clock interface as provided in CM_WKUP_DEBUGSS_CLKCTRL register, which includes, - Clock gate for optional DEBUG_CLKA and DBGSYSCLK - Clock Mux for TRC_PMD and STM_PMD - Clock divider for STM and TPIU Signed-off-by: Vaibhav Hiremath Cc: Kevin Hilman Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rajendra Nayak Acked-by: Paul Walmsley --- arch/arm/mach-omap2/cclock33xx_data.c | 47 +++++++++++++++++++++++++++++--- 1 files changed, 42 insertions(+), 5 deletions(-) -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 3d5a0e5..12db88c 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -422,15 +422,11 @@ DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); * - Driver code is not yet migrated to use hwmod/runtime pm * - Modules outside kernel access (to disable them by default) * - * - debugss * - mmu (gfx domain) * - cefuse * - usbotg_fck (its additional clock and not really a modulemode) * - ieee5000 */ -DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, @@ -833,6 +829,42 @@ static struct clk_hw_omap wdt1_fck_hw = { DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); /* + * debugss optional clocks + */ +DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, + 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, + 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); + +static const char *stm_pmd_clock_mux_ck_parents[] = { + "dbg_sysclk_ck", "dbg_clka_ck", +}; + +DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, + AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_TRC_PMD_CLKSEL_SHIFT, + AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", + &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_STM_PMD_CLKDIVSEL_SHIFT, + AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", + &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, + AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +/* * clkdev */ static struct omap_clk am33xx_clks[] = { @@ -869,7 +901,6 @@ static struct omap_clk am33xx_clks[] = { CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), - CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), @@ -910,6 +941,12 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck, CK_AM33XX), + CLK(NULL, "dbg_clka_ck", &dbg_clka_ck, CK_AM33XX), + CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck, CK_AM33XX), + CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck, CK_AM33XX), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_AM33XX), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_AM33XX), };