From patchwork Sat Mar 16 06:16:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 2281601 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id C9673DF5B1 for ; Sat, 16 Mar 2013 06:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754136Ab3CPGSt (ORCPT ); Sat, 16 Mar 2013 02:18:49 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38662 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752780Ab3CPGRC (ORCPT ); Sat, 16 Mar 2013 02:17:02 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2G6GwpV011079; Sat, 16 Mar 2013 01:16:58 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2G6GvIt014987; Sat, 16 Mar 2013 11:46:57 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Sat, 16 Mar 2013 11:46:57 +0530 Received: from a0131933lt.itg.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2G6Gnm2003136; Sat, 16 Mar 2013 11:46:55 +0530 From: Lokesh Vutla To: CC: , , , , , Ambresh K , Nishanth Menon Subject: [PATCH V2 2/8] memory: emif: setup LP settings on freq update Date: Sat, 16 Mar 2013 11:46:42 +0530 Message-ID: <1363414608-7448-3-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363414608-7448-1-git-send-email-lokeshvutla@ti.com> References: <1363414608-7448-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Ambresh K Program the power management shadow register on freq update Else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: Nishanth Menon Signed-off-by: Ambresh K Signed-off-by: Lokesh Vutla Acked-by: Santosh Shilimkar --- Changes since V1: No changes drivers/memory/emif.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c index 508763c..5f3b7ed 100644 --- a/drivers/memory/emif.c +++ b/drivers/memory/emif.c @@ -819,6 +819,8 @@ static void setup_registers(struct emif_data *emif, struct emif_regs *regs) writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); + writel(regs->pwr_mgmt_ctrl_shdw, + base + EMIF_POWER_MANAGEMENT_CTRL_SHDW); /* Settings specific for EMIF4D5 */ if (emif->plat_data->ip_rev != EMIF_4D5)