From patchwork Mon Mar 25 07:27:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 2329171 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 126053FD8C for ; Mon, 25 Mar 2013 07:28:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755318Ab3CYH2P (ORCPT ); Mon, 25 Mar 2013 03:28:15 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:56856 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754168Ab3CYH2N (ORCPT ); Mon, 25 Mar 2013 03:28:13 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2P7S7YU014196; Mon, 25 Mar 2013 02:28:07 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2P7S4si011402; Mon, 25 Mar 2013 12:58:06 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Mon, 25 Mar 2013 12:58:04 +0530 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2P7S1eM022275; Mon, 25 Mar 2013 12:58:04 +0530 From: Mugunthan V N To: CC: , , , , Mugunthan V N Subject: [PATCH 2/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk Date: Mon, 25 Mar 2013 12:57:57 +0530 Message-ID: <1364196478-16688-3-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1364196478-16688-1-git-send-email-mugunthanvnm@ti.com> References: <1364196478-16688-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add pinmux configurations for RGMII based CPSW ethernet to am335x-evmsk. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am335x-evmsk.dts | 38 +++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index f297b85..9b29ad4 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -32,7 +32,7 @@ am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>; + pinctrl-0 = <&user_leds_s0 &gpio_keys_s0 &cpsw_s0>; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < @@ -51,6 +51,42 @@ 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */ >; }; + + cpsw_s0: cpsw_s0 { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2 | OUTPUT */ + 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2 | INPUT_PULLDOWN */ + 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2 | OUTPUT */ + 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2 | OUTPUT */ + 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2 | OUTPUT */ + 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2 | OUTPUT */ + 0x12c 0x2 /* mii1_txclk.rgmii1_tclk, MODE2 | OUTPUT */ + 0x130 0x22 /* mii1_rxclk.rgmii1_rclk, MODE2 | INPUT_PULLDOWN */ + 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2 | INPUT_PULLDOWN */ + 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2 | INPUT_PULLDOWN */ + 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2 | INPUT_PULLDOWN */ + 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2 | INPUT_PULLDOWN */ + + /* Slave 2 */ + 0x40 0x2 /* gpmc_a0.rgmii2_tctl", MODE2 | OUTPUT */ + 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2 | INPUT_PULLDOWN */ + 0x48 0x2 /* gpmc_a2.rgmii2_td3", MODE2 | OUTPUT */ + 0x4c 0x2 /* gpmc_a3.rgmii2_td2", MODE2 | OUTPUT */ + 0x50 0x2 /* gpmc_a4.rgmii2_td1", MODE2 | OUTPUT */ + 0x54 0x2 /* gpmc_a5.rgmii2_td0", MODE2 | OUTPUT */ + 0x58 0x2 /* gpmc_a6.rgmii2_tclk", MODE2 | OUTPUT */ + 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2 | INPUT_PULLDOWN */ + 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 | INPUT_PULLDOWN */ + 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 | INPUT_PULLDOWN */ + 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2 | INPUT_PULLDOWN */ + 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2 | INPUT_PULLDOWN */ + + /* MDIO */ + 0x148 0x30 /* mdio_data.mdio_data, MODE0 | INPUT_PULLUP */ + 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 | OUTPUT_PULLUP */ + >; + }; }; ocp {