From patchwork Fri May 3 07:38:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 2516111 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id A1E25DF2E5 for ; Fri, 3 May 2013 07:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932986Ab3ECHjT (ORCPT ); Fri, 3 May 2013 03:39:19 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33080 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932971Ab3ECHjR (ORCPT ); Fri, 3 May 2013 03:39:17 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r437dC3V018103; Fri, 3 May 2013 02:39:12 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r437dCeA021534; Fri, 3 May 2013 02:39:12 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Fri, 3 May 2013 02:39:11 -0500 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r437d5w1004833; Fri, 3 May 2013 02:39:09 -0500 From: Mugunthan V N To: CC: , , , , , Hebbar Gururaja , Mugunthan V N Subject: [net-next PATCH 1/6] net: cpsw: enhance pinctrl support Date: Fri, 3 May 2013 13:08:51 +0530 Message-ID: <1367566736-26644-2-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1367566736-26644-1-git-send-email-mugunthanvnm@ti.com> References: <1367566736-26644-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Hebbar Gururaja Amend cpsw controller to optionally take a pin control handle and set the state of the pins to: - "default" on boot, resume - "sleep" on suspend() This should make it possible to optimize energy usage for the pins for the suspend/resume cycle. If any of the above pin states are missing in dt, a warning message about the missing state is displayed. If certain pin-states are not available, to remove this warning message pass respective state name with null phandler. Signed-off-by: Hebbar Gururaja Signed-off-by: Mugunthan V N --- drivers/net/ethernet/ti/cpsw.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 21a5b29..4a6f94b 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -35,6 +35,7 @@ #include #include +#include #include "cpsw_ale.h" #include "cpts.h" @@ -351,6 +352,11 @@ struct cpsw_priv { bool irq_enabled; struct cpts *cpts; u32 emac_port; + + /* Two optional pin states - default & sleep */ + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; }; #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) @@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev) */ pm_runtime_enable(&pdev->dev); + priv->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR(priv->pinctrl)) { + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, + PINCTRL_STATE_DEFAULT); + /* enable pins to be muxed in and configured */ + if (IS_ERR(priv->pins_default)) + dev_warn(&pdev->dev, "could not get default pinstate\n"); + else + if (pinctrl_select_state(priv->pinctrl, + priv->pins_default)) + dev_err(&pdev->dev, + "could not set default pins\n"); + + priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl, + PINCTRL_STATE_SLEEP); + if (IS_ERR(priv->pins_sleep)) + dev_warn(&pdev->dev, "could not get sleep pinstate\n"); + } else { + /* + * Since we continue even when pinctrl node is not found, + * Invalidate pins as not available. This is to make sure that + * IS_ERR(pins_xxx) results in failure when used. + */ + priv->pins_default = ERR_PTR(-ENODATA); + priv->pins_sleep = ERR_PTR(-ENODATA); + + dev_warn(&pdev->dev, + "pins are not configured from the driver\n"); + } + if (cpsw_probe_dt(&priv->data, pdev)) { pr_err("cpsw: platform data missing\n"); ret = -ENODEV; @@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct net_device *ndev = platform_get_drvdata(pdev); + struct cpsw_priv *priv = netdev_priv(ndev); if (netif_running(ndev)) cpsw_ndo_stop(ndev); pm_runtime_put_sync(&pdev->dev); + /* Optionally let pins go into sleep states */ + if (!IS_ERR(priv->pins_sleep)) + if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep)) + dev_err(dev, "could not set pins to sleep state\n"); + return 0; } @@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct net_device *ndev = platform_get_drvdata(pdev); + struct cpsw_priv *priv = netdev_priv(ndev); pm_runtime_get_sync(&pdev->dev); + + /* Optionaly enable pins to be muxed in and configured */ + if (!IS_ERR(priv->pins_default)) + if (pinctrl_select_state(priv->pinctrl, priv->pins_default)) + dev_err(dev, "could not set default pins\n"); + if (netif_running(ndev)) cpsw_ndo_open(ndev); return 0;