From patchwork Sun May 26 18:23:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 2616781 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 1D3FCDFB79 for ; Sun, 26 May 2013 18:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754670Ab3EZSXg (ORCPT ); Sun, 26 May 2013 14:23:36 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:51146 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754839Ab3EZSXF (ORCPT ); Sun, 26 May 2013 14:23:05 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r4QIN0Mm017238; Sun, 26 May 2013 13:23:00 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r4QIN0Fs011531; Sun, 26 May 2013 13:23:00 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Sun, 26 May 2013 13:22:59 -0500 Received: from a0131834-linux.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r4QIMgPN011073; Sun, 26 May 2013 13:22:57 -0500 From: Mugunthan V N To: CC: , , , , , Mugunthan V N Subject: [net-next PATCH v3 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk Date: Sun, 26 May 2013 23:53:35 +0530 Message-ID: <1369592616-23972-6-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369592616-23972-1-git-send-email-mugunthanvnm@ti.com> References: <1369592616-23972-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk. In this patch, only single named mode/state is added and these pins are configured during pinctrl driver initialization. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Todo: - if an idle state is available for pins, add support for it. Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am335x-evmsk.dts | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index acbcac3..12cbe4e 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -51,6 +51,46 @@ 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */ >; }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2 | OUTPUT */ + 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2 | INPUT_PULLDOWN */ + 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2 | OUTPUT */ + 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2 | OUTPUT */ + 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2 | OUTPUT */ + 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2 | OUTPUT */ + 0x12c 0x2 /* mii1_txclk.rgmii1_tclk, MODE2 | OUTPUT */ + 0x130 0x22 /* mii1_rxclk.rgmii1_rclk, MODE2 | INPUT_PULLDOWN */ + 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2 | INPUT_PULLDOWN */ + 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2 | INPUT_PULLDOWN */ + 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2 | INPUT_PULLDOWN */ + 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2 | INPUT_PULLDOWN */ + + /* Slave 2 */ + 0x40 0x2 /* gpmc_a0.rgmii2_tctl", MODE2 | OUTPUT */ + 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2 | INPUT_PULLDOWN */ + 0x48 0x2 /* gpmc_a2.rgmii2_td3", MODE2 | OUTPUT */ + 0x4c 0x2 /* gpmc_a3.rgmii2_td2", MODE2 | OUTPUT */ + 0x50 0x2 /* gpmc_a4.rgmii2_td1", MODE2 | OUTPUT */ + 0x54 0x2 /* gpmc_a5.rgmii2_td0", MODE2 | OUTPUT */ + 0x58 0x2 /* gpmc_a6.rgmii2_tclk", MODE2 | OUTPUT */ + 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2 | INPUT_PULLDOWN */ + 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 | INPUT_PULLDOWN */ + 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 | INPUT_PULLDOWN */ + 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2 | INPUT_PULLDOWN */ + 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2 | INPUT_PULLDOWN */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 0x30 /* mdio_data.mdio_data, MODE0 | INPUT_PULLUP */ + 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 | OUTPUT_PULLUP */ + >; + }; }; ocp { @@ -249,6 +289,16 @@ }; }; +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; };