From patchwork Thu May 30 08:50:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jean-Philippe_Fran=C3=83=C2=A7ois?= X-Patchwork-Id: 2634161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 62B84DF2A1 for ; Thu, 30 May 2013 08:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967959Ab3E3Iuv (ORCPT ); Thu, 30 May 2013 04:50:51 -0400 Received: from mail-we0-f169.google.com ([74.125.82.169]:49839 "EHLO mail-we0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967252Ab3E3Iut (ORCPT ); Thu, 30 May 2013 04:50:49 -0400 Received: by mail-we0-f169.google.com with SMTP id q55so7213504wes.14 for ; Thu, 30 May 2013 01:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=x7q4K5LKeOcnAgDgBGQimtHk7b9hT50kyZPJrFzkpOY=; b=zdh8uYvTWCJhE1KGJ4bp8Oc/W8YyuPsh/sFu3cFAIf/jHeI4+XL7NTbAnpRyNGDlaL zjxkvc06U5tthzqBvzWGrFQ1BM1UGhJtKwHiJC+Tb4gYUhw+k1kj4DjHiLVrKu8yTaTF 40wSRAqLbQrxjtc/JYjZd+H7DKMl88MkDORcOXMpNy1l7QaCtVsZfxXYiCCVtEOuYEKj xfhbNTIZ9/v8vYUuWdImg9eLzdruMNyJOtvFIDpklyupWyD3xzt7Y5g26wvUekxRknTS oBQqFTvk5bjWPP1VeD6Uthlv4GY2xyXPd22P7EgeLxHuxwEC8GxpYhoI2TMUmpU+2FpO gh3Q== X-Received: by 10.180.206.9 with SMTP id lk9mr16721721wic.0.1369903847994; Thu, 30 May 2013 01:50:47 -0700 (PDT) Received: from localhost.localdomain (vil35-1-82-67-117-55.fbx.proxad.net. [82.67.117.55]) by mx.google.com with ESMTPSA id ca19sm36441795wib.3.2013.05.30.01.50.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 30 May 2013 01:50:47 -0700 (PDT) From: Jean-Philippe Francois To: paul@pwsan.com, tony@atomide.com, mturquette@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, =?UTF-8?q?Jean-Philippe=20Fran=C3=A7ois?= Subject: [PATCH v2 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c Date: Thu, 30 May 2013 10:50:27 +0200 Message-Id: <1369903827-2025-1-git-send-email-jp.francois@cynove.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock have parent defined as clk_divider. Instead of using container_of to eventually get to the register and directly mess with the divider, change freq via clk_set_rate, and let the clock framework toggle the divider value. Tested with 3.9 on dm3730. Signed-off-by: Jean-Philippe François Acked-by: Mike Turquette --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: b/arch/arm/mach-omap2/clock36xx.c =================================================================== --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -39,30 +39,25 @@ */ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { - struct clk_hw_omap *parent; - struct clk_hw *parent_hw; - u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); - parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); - parent = to_clk_hw_omap(parent_hw); - - /* Restore the dividers */ + /* kick parent's clksel register after toggling PWRDN bit */ if (!ret) { - clksel_shift = __ffs(parent->clksel_mask); - orig_v = __raw_readl(parent->clksel_reg); - dummy_v = orig_v; - - /* Write any other value different from the Read value */ - dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, parent->clksel_reg); - - /* Write the original divider */ - __raw_writel(orig_v, parent->clksel_reg); + struct clk *parent = clk_get_parent(clk->clk); + unsigned long parent_rate = clk_get_rate(parent); + ret = clk_set_rate(parent, parent_rate/2); + if(ret) + goto badfreq; + ret = clk_set_rate(parent, parent_rate); + if(ret) + goto badfreq; } + return ret; + badfreq : + omap2_dflt_clk_disable(clk); return ret; }