From patchwork Tue Jun 11 10:02:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 2701091 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 3803A40077 for ; Tue, 11 Jun 2013 10:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754118Ab3FKKA5 (ORCPT ); Tue, 11 Jun 2013 06:00:57 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:43207 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753741Ab3FKKAz (ORCPT ); Tue, 11 Jun 2013 06:00:55 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5BA0sLs009241; Tue, 11 Jun 2013 05:00:54 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5BA0ssV025015; Tue, 11 Jun 2013 05:00:54 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Tue, 11 Jun 2013 05:00:53 -0500 Received: from a0131834-linux.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r5BA0lpG012476; Tue, 11 Jun 2013 05:00:52 -0500 From: Mugunthan V N To: CC: , , Mugunthan V N Subject: [net PATCH 2/2] drivers: net: davinci_mdio: restore mdio clk divider in mdio resume Date: Tue, 11 Jun 2013 15:32:05 +0530 Message-ID: <1370944925-11374-3-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370944925-11374-1-git-send-email-mugunthanvnm@ti.com> References: <1370944925-11374-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org During suspend resume cycle all the register data is lost, so MDIO clock divier value gets reset. This patch restores the clock divider value. Signed-off-by: Mugunthan V N --- drivers/net/ethernet/ti/davinci_mdio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c index 74e56b3..c47f0db 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -459,15 +459,12 @@ static int davinci_mdio_suspend(struct device *dev) static int davinci_mdio_resume(struct device *dev) { struct davinci_mdio_data *data = dev_get_drvdata(dev); - u32 ctrl; pm_runtime_get_sync(data->dev); spin_lock(&data->lock); /* restart the scan state machine */ - ctrl = __raw_readl(&data->regs->control); - ctrl |= CONTROL_ENABLE; - __raw_writel(ctrl, &data->regs->control); + __davinci_mdio_reset(data); data->suspended = false; spin_unlock(&data->lock);