From patchwork Wed Jun 19 13:18:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2749161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7354E9F3A0 for ; Wed, 19 Jun 2013 13:19:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 42AC12028A for ; Wed, 19 Jun 2013 13:19:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C13612026D for ; Wed, 19 Jun 2013 13:19:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756677Ab3FSNTk (ORCPT ); Wed, 19 Jun 2013 09:19:40 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39501 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756732Ab3FSNTi (ORCPT ); Wed, 19 Jun 2013 09:19:38 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5JDJCpi001944; Wed, 19 Jun 2013 08:19:12 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5JDJCQA026158; Wed, 19 Jun 2013 08:19:12 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 19 Jun 2013 08:19:12 -0500 Received: from sokoban.tieu.ti.com (h79-27.vpn.ti.com [172.24.79.27]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r5JDJ40X024678; Wed, 19 Jun 2013 08:19:10 -0500 From: Tero Kristo To: , , , , , CC: , Subject: [PATCHv2 02/11] CLK: use of_property_read_u32 instead of read_u8 Date: Wed, 19 Jun 2013 16:18:53 +0300 Message-ID: <1371647942-4811-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371647942-4811-1-git-send-email-t-kristo@ti.com> References: <1371647942-4811-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP of_property_read_u8 does not work properly because of endianess problem with its current implementation, and this causes it to always return 0 with little endian architectures. Instead, use property_read_u32 until this is fixed. Signed-off-by: Tero Kristo --- drivers/clk/clk-divider.c | 4 ++-- drivers/clk/clk-gate.c | 4 ++-- drivers/clk/clk-mux.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 17ea475..3413602 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -361,7 +361,7 @@ void of_divider_clk_setup(struct device_node *node) const char *parent_name; u8 clk_divider_flags = 0; u32 mask = 0; - u8 shift = 0; + u32 shift = 0; struct clk_div_table *table; of_property_read_string(node, "clock-output-names", &clk_name); @@ -375,7 +375,7 @@ void of_divider_clk_setup(struct device_node *node) return; } - if (of_property_read_u8(node, "bit-shift", &shift)) { + if (of_property_read_u32(node, "bit-shift", &shift)) { shift = __ffs(mask); pr_debug("%s: bit-shift property defaults to 0x%x for %s\n", __func__, shift, node->name); diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 72cf99d..61b4dc1 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -162,7 +162,7 @@ void of_gate_clk_setup(struct device_node *node) void __iomem *reg; const char *parent_name; u8 clk_gate_flags = 0; - u8 bit_idx = 0; + u32 bit_idx = 0; of_property_read_string(node, "clock-output-names", &clk_name); @@ -170,7 +170,7 @@ void of_gate_clk_setup(struct device_node *node) reg = of_iomap(node, 0); - if (of_property_read_u8(node, "bit-shift", &bit_idx)) { + if (of_property_read_u32(node, "bit-shift", &bit_idx)) { pr_err("%s: missing bit-shift property for %s\n", __func__, node->name); return; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index c9f9f32..e63dd1b 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -170,7 +170,7 @@ void of_mux_clk_setup(struct device_node *node) int i; u8 clk_mux_flags = 0; u32 mask = 0; - u8 shift = 0; + u32 shift = 0; of_property_read_string(node, "clock-output-names", &clk_name); @@ -194,7 +194,7 @@ void of_mux_clk_setup(struct device_node *node) return; } - if (of_property_read_u8(node, "bit-shift", &shift)) { + if (of_property_read_u32(node, "bit-shift", &shift)) { shift = __ffs(mask); pr_debug("%s: bit-shift property defaults to 0x%x for %s\n", __func__, shift, node->name);