From patchwork Tue Jul 2 11:28:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Bedia X-Patchwork-Id: 2812491 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A8E71BF4A1 for ; Tue, 2 Jul 2013 11:29:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C82EF201E7 for ; Tue, 2 Jul 2013 11:29:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B5413201E3 for ; Tue, 2 Jul 2013 11:29:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752347Ab3GBL30 (ORCPT ); Tue, 2 Jul 2013 07:29:26 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:41804 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752334Ab3GBL30 (ORCPT ); Tue, 2 Jul 2013 07:29:26 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r62BSlvS029198; Tue, 2 Jul 2013 06:28:47 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r62BSk6i025253; Tue, 2 Jul 2013 06:28:46 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Tue, 2 Jul 2013 06:28:46 -0500 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r62BSdw8030121; Tue, 2 Jul 2013 06:28:44 -0500 From: Vaibhav Bedia To: , CC: , , , Vaibhav Bedia Subject: [RFC 2/9] ARM: OMAP2+: CM code: Reintroduce SW_SLEEP for OMAP4 class of devices Date: Tue, 2 Jul 2013 16:58:11 +0530 Message-ID: <1372764498-32503-3-git-send-email-vaibhav.bedia@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1372764498-32503-1-git-send-email-vaibhav.bedia@ti.com> References: <1372764498-32503-1-git-send-email-vaibhav.bedia@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 65aa94b (ARM: OMAP4: clockdomain/CM code: Update supported transition modes) removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not having SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the way of other devices like AM335x which have the same hardware underneath but support only SW_SLEEP/SW_WKUP modes. So far, AM335x has been uses its own set of PRM/CM APIs and hence the lack of SW_SLEEP mode in the OMAP4 code was not a problem. However we would like to consolidate the AM335x and OMAP4 code and reintroducing this mode is necessary. Doing so also makes the API consistent with what the comments states. While here also fixup a trivial typo in the comment. Signed-off-by: Vaibhav Bedia --- arch/arm/mach-omap2/cminst44xx.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index f0290f5..2d1d4ef 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -237,7 +237,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) } /** - * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle + * omap4_cminst_clkdm_force_wakeup - try to take a clockdomain out of idle * @part: PRCM partition ID that the clockdomain registers exist in * @inst: CM instance register offset (*_INST macro) * @cdoffs: Clockdomain register offset (*_CDOFFS macro) @@ -250,6 +250,20 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); } +/** + * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle, + * forcing it to sleep. No return value. + */ +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); +} + /* * */ @@ -404,7 +418,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) static int omap4_clkdm_sleep(struct clockdomain *clkdm) { - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, clkdm->cm_inst, clkdm->clkdm_offs); return 0; }