From patchwork Thu Jul 18 10:01:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Poddar, Sourav" X-Patchwork-Id: 2829575 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 32CED9F9EB for ; Thu, 18 Jul 2013 10:02:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13521201E4 for ; Thu, 18 Jul 2013 10:02:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D3AC2201D7 for ; Thu, 18 Jul 2013 10:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758240Ab3GRKB5 (ORCPT ); Thu, 18 Jul 2013 06:01:57 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36012 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754902Ab3GRKBx (ORCPT ); Thu, 18 Jul 2013 06:01:53 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6IA1iTG019482; Thu, 18 Jul 2013 05:01:44 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6IA1ix7013170; Thu, 18 Jul 2013 05:01:44 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Thu, 18 Jul 2013 05:01:43 -0500 Received: from a0131647.apr.dhcp.ti.com (a0131647.apr.dhcp.ti.com [172.24.145.168]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6IA1TIT001181; Thu, 18 Jul 2013 05:01:41 -0500 From: Sourav Poddar To: , , CC: , , , , Sourav Poddar Subject: [RFC/PATCHv2 3/3] driver: spi: Add quad spi read support Date: Thu, 18 Jul 2013 15:31:27 +0530 Message-ID: <1374141687-10790-4-git-send-email-sourav.poddar@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1374141687-10790-1-git-send-email-sourav.poddar@ti.com> References: <1374141687-10790-1-git-send-email-sourav.poddar@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs dual or quad lines. This patch has been done on top of the following patch[1], which is just the basic idea of adding dual/quad support in spi framework. $subject patch will undergo changes as the parent patch goes[1] [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Signed-off-by: Sourav Poddar --- v1->v2 Added support for dual also. drivers/spi/spi-ti-qspi.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 3cae731..3a5c56d 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -86,6 +86,7 @@ struct ti_qspi { #define QSPI_3_PIN (1 << 18) #define QSPI_RD_SNGL (1 << 16) #define QSPI_WR_SNGL (2 << 16) +#define QSPI_RD_DUAL (3 << 16) #define QSPI_RD_QUAD (7 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_WC_CMD_INT_EN (1 << 14) @@ -280,6 +281,7 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) { u8 *rxbuf; int wlen, count; + unsigned cmd = qspi->cmd; count = t->len; rxbuf = t->rx_buf; @@ -289,8 +291,19 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", qspi->cmd | QSPI_RD_SNGL, qspi->dc); ti_qspi_writel(qspi, qspi->dc, QSPI_SPI_DC_REG); - ti_qspi_writel(qspi, qspi->cmd | QSPI_RD_SNGL, - QSPI_SPI_CMD_REG); + switch (t->bitwidth) { + case SPI_BITWIDTH_QUAD: + cmd |= QSPI_RD_QUAD; + break; + case SPI_BITWIDTH_DUAL: + cmd |= QSPI_RD_DUAL; + break; + case SPI_BITWIDTH_SINGLE: + default: + cmd |= QSPI_RD_SNGL; + } + + ti_qspi_writel(qspi, cmd, QSPI_SPI_CMD_REG); ti_qspi_writel(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); wait_for_completion(&qspi->transfer_complete); *rxbuf++ = ti_qspi_readl_data(qspi, QSPI_SPI_DATA_REG, wlen);