From patchwork Mon Jul 29 07:22:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Poddar, Sourav" X-Patchwork-Id: 2834843 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9341B9F9D9 for ; Mon, 29 Jul 2013 07:22:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AA16420258 for ; Mon, 29 Jul 2013 07:22:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C800020251 for ; Mon, 29 Jul 2013 07:22:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754120Ab3G2HWz (ORCPT ); Mon, 29 Jul 2013 03:22:55 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:47530 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750767Ab3G2HWy (ORCPT ); Mon, 29 Jul 2013 03:22:54 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6T7MgAu013028; Mon, 29 Jul 2013 02:22:42 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6T7MgqN027137; Mon, 29 Jul 2013 02:22:42 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Mon, 29 Jul 2013 02:22:42 -0500 Received: from a0131647.apr.dhcp.ti.com (a0131647.apr.dhcp.ti.com [172.24.145.168]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6T7MWnh002372; Mon, 29 Jul 2013 02:22:40 -0500 From: Sourav Poddar To: , , CC: , , , Sourav Poddar Subject: [RFC/PATCH 2/2] driver: spi: Add quad spi read support Date: Mon, 29 Jul 2013 12:52:30 +0530 Message-ID: <1375082550-30544-3-git-send-email-sourav.poddar@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1375082550-30544-1-git-send-email-sourav.poddar@ti.com> References: <1375082550-30544-1-git-send-email-sourav.poddar@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since, qspi controller uses quad read. Configuring the command register, if the transfer of data needs dual or quad lines. This patch has been done on top of the following patch[1], which is just the basic idea of adding dual/quad support in spi framework. $subject patch will undergo changes with the ongoing discussion in the community. This patch is posted to demonstrate how patch 1 of the series will support quad read. [1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047 Signed-off-by: Sourav Poddar --- drivers/spi/spi-ti-qspi.c | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 51fe95f..8a32b1c 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -86,6 +86,7 @@ struct ti_qspi { #define QSPI_3_PIN (1 << 18) #define QSPI_RD_SNGL (1 << 16) #define QSPI_WR_SNGL (2 << 16) +#define QSPI_RD_DUAL (3 << 16) #define QSPI_RD_QUAD (7 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_WC_CMD_INT_EN (1 << 14) @@ -264,6 +265,7 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) { u8 *rxbuf; int wlen, count; + unsigned cmd = qspi->cmd; count = t->len; rxbuf = t->rx_buf; @@ -273,8 +275,18 @@ static void qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", qspi->cmd | QSPI_RD_SNGL, qspi->dc); ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); - ti_qspi_write(qspi, qspi->cmd | QSPI_RD_SNGL, - QSPI_SPI_CMD_REG); + switch (t->bitwidth) { + case SPI_BITWIDTH_QUAD: + cmd |= QSPI_RD_QUAD; + break; + case SPI_BITWIDTH_DUAL: + cmd |= QSPI_RD_DUAL; + break; + case SPI_BITWIDTH_SINGLE: + default: + cmd |= QSPI_RD_SNGL; + } + ti_qspi_writel(qspi, cmd, QSPI_SPI_CMD_REG); ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); wait_for_completion(&qspi->transfer_complete); ti_qspi_read_data(qspi, QSPI_SPI_DATA_REG, wlen, &rxbuf);