From patchwork Thu Aug 8 10:14:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 2840951 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 75B58BF535 for ; Thu, 8 Aug 2013 10:14:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4B53E20417 for ; Thu, 8 Aug 2013 10:14:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F162E20399 for ; Thu, 8 Aug 2013 10:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934200Ab3HHKOu (ORCPT ); Thu, 8 Aug 2013 06:14:50 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:49140 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934178Ab3HHKOt (ORCPT ); Thu, 8 Aug 2013 06:14:49 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r78AENXH021456; Thu, 8 Aug 2013 05:14:23 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r78AENYD022130; Thu, 8 Aug 2013 05:14:23 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 8 Aug 2013 05:14:23 -0500 Received: from ula0131687.apr.dhcp.ti.com (aartee-desktop-172024145038.apr.dhcp.ti.com [172.24.145.38]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r78AEL8Z031090; Thu, 8 Aug 2013 05:14:21 -0500 From: Rajendra Nayak To: , CC: , , Rajendra Nayak Subject: [PATCH] ARM: OMAP4: clock: Lock PLLs in the right sequence Date: Thu, 8 Aug 2013 15:44:11 +0530 Message-ID: <1375956851-842-1-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On OMAP4 we have clk_set_rate()s being done for a few DPLL clock nodes, as part of the clock init code, since the bootloaders no longer locks these DPLLs. So we have a clk_set_rate() done for a ABE DPLL node (which inturn locks it) followed by a clk_set_rate() for the USB DPLL. With USB DPLL being in bypass, we have this parent->child relationship thats formed while the clocks get registered. dpll_abe_ck | V dpll_abe_x2_ck | V dpll_abe_m3x2_ck | V usb_hs_clk_div_ck | V dpll_usb_ck This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck. So with this parent->child relationship in place, a clk_set_rate() on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL, because CCF does a clk_change_rate() (as part of clk_set_rate()) on all downstream clocks resulting from a rate change on the top clock. So its important that we lock USB DPLL before we lock ABE DPLL. Without which we see these error logs at boot. [These error logs will not be seen if using a bootloader that locks USB DPLL] [ 0.000000] clock: dpll_usb_ck failed transition to 'locked' [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck [ 0.000000] Division by zero in kernel. Signed-off-by: Rajendra Nayak --- arch/arm/mach-omap2/cclock44xx_data.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 88e37a4..1d5b529 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void) omap2_clk_disable_autoidle_all(); /* + * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL + * when its in bypass. So always lock USB before ABE DPLL. + */ + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + + /* * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power * state when turning the ABE clock domain. Workaround this by * locking the ABE DPLL on boot. @@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - /* - * Lock USB DPLL on OMAP4 devices so that the L3INIT power - * domain can transition to retention state when not in use. - */ - rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); - if (rc) - pr_err("%s: failed to configure USB DPLL!\n", __func__); - return 0; }