From patchwork Sun Aug 11 16:17:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 2842717 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 501D5BF546 for ; Sun, 11 Aug 2013 16:18:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6971620221 for ; Sun, 11 Aug 2013 16:18:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 229192021A for ; Sun, 11 Aug 2013 16:18:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754190Ab3HKQSi (ORCPT ); Sun, 11 Aug 2013 12:18:38 -0400 Received: from ring0.de ([91.143.88.219]:44556 "EHLO smtp.ring0.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754185Ab3HKQSh (ORCPT ); Sun, 11 Aug 2013 12:18:37 -0400 Received: from comu.ring0.de (unknown [127.0.0.1]) by smtp.ring0.de (Postfix) with ESMTP id E00472C58FA3; Sun, 11 Aug 2013 18:18:34 +0200 (CEST) Received: (from spamd@localhost) by comu.ring0.de (8.13.8/8.13.8/Submit) id r7BGIYQp032550; Sun, 11 Aug 2013 18:18:34 +0200 X-Authentication-Warning: comu.ring0.de: spamd set sender to sre@ring0.de using -f X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from sre.ring0.de (unknown [83.68.216.121]) by smtp.ring0.de (Postfix) with ESMTP id 504162C58F9C; Sun, 11 Aug 2013 18:18:12 +0200 (CEST) From: Sebastian Reichel To: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org, linus.walleij@linaro.org, Kevin Hilman , Shubhrajyoti Datta , Carlos Chinea , Sebastian Reichel Subject: [PATCH 1/3] ARM: OMAP2+: hwmod-data: Add SSI information Date: Sun, 11 Aug 2013 18:17:55 +0200 Message-Id: <1376237877-1740-1-git-send-email-sre@debian.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1376237628-1077-1-git-send-email-sre@debian.org> References: <1376237628-1077-1-git-send-email-sre@debian.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sebastian Reichel This patch adds Synchronous Serial Interface (SSI) hwmod support for OMAP34xx SoCs. --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 104 ++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 0c3a427..74006c4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -3693,6 +3693,109 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* + * 'ssi' class + * synchronous serial interface (multichannel and full-duplex serial if) + */ + +static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | + SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap34xx_ssi_hwmod_class = { + .name = "ssi", + .sysc = &omap34xx_ssi_sysc, +}; + +static struct omap_hwmod_irq_info omap34xx_ssi_irqs[] = { + { .name = "ssi_p1_mpu_irq0", .irq = 67 }, + { .name = "ssi_p1_mpu_irq1", .irq = 68 }, + { .name = "ssi_p2_mpu_irq0", .irq = 69 }, + { .name = "ssi_p2_mpu_irq1", .irq = 70 }, + { .name = "ssi_gdd_mpu", .irq = 71 }, + { .irq = -1 }, +}; + +static struct omap_hwmod_addr_space omap34xx_ssi_addrs[] = { + { + .name = "sys", + .pa_start = 0x48058000, + .pa_end = 0x48058fff, + .flags = ADDR_TYPE_RT, + }, + { + /* generic distributed DMA */ + .name = "gdd", + .pa_start = 0x48059000, + .pa_end = 0x48059fff, + .flags = ADDR_TYPE_RT, + }, + { + /* port 1: synchronous serial transmitter */ + .name = "p1_sst", + .pa_start = 0x4805a000, + .pa_end = 0x4805a7ff, + .flags = ADDR_TYPE_RT, + }, + { + /* port 1: synchronous serial receiver */ + .name = "p1_ssr", + .pa_start = 0x4805a800, + .pa_end = 0x4805afff, + .flags = ADDR_TYPE_RT, + }, + { + /* port 2: synchronous serial transmitter */ + .name = "p2_sst", + .pa_start = 0x4805b000, + .pa_end = 0x4805b7ff, + .flags = ADDR_TYPE_RT, + }, + { + /* port 2: synchronous serial receiver */ + .name = "p2_ssr", + .pa_start = 0x4805b800, + .pa_end = 0x4805bfff, + .flags = ADDR_TYPE_RT, + }, + {} +}; + +static struct omap_hwmod omap34xx_ssi_hwmod = { + .name = "ssi", + .class = &omap34xx_ssi_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap34xx_ssi_irqs, + .main_clk = "ssi_ssr_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SSI_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, + }, + }, +}; + +/* SSI -> l3 */ +static struct omap_hwmod_ocp_if omap34xx_l3__ssi = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap34xx_ssi_hwmod, + .clk = "ssi_ick", + .addr = omap34xx_ssi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3818,6 +3921,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { #ifdef CONFIG_OMAP_IOMMU_IVA2 &omap3xxx_l3_main__mmu_iva, #endif + &omap34xx_l3__ssi, NULL };