From patchwork Tue Aug 13 22:20:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Dill X-Patchwork-Id: 2844046 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 86E999F2F6 for ; Tue, 13 Aug 2013 22:20:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ADC71202BE for ; Tue, 13 Aug 2013 22:20:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CE6B42040F for ; Tue, 13 Aug 2013 22:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759383Ab3HMWUW (ORCPT ); Tue, 13 Aug 2013 18:20:22 -0400 Received: from mail-oa0-f50.google.com ([209.85.219.50]:36196 "EHLO mail-oa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759255Ab3HMWUT (ORCPT ); Tue, 13 Aug 2013 18:20:19 -0400 Received: by mail-oa0-f50.google.com with SMTP id i4so12105111oah.23 for ; Tue, 13 Aug 2013 15:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=RfnFz/d1WxxVGCO3QI3bOpVISp4rjwdnQAMbLZrDWHQ=; b=VneYIT/LoFEjHZPmFt3u5xwaMnEgbUXFlQEnFUMOovSwa9b/cfnbVz+LWmFsG5IHfZ gtQ51GW4Y8REhHRPWV2flxPoYlpCtc1Cibk/OMqMw0LgAK3mthVLrg0fjI57nuCoMzOj kSHoVdZuODhND0Jv/uD34WsoDCBuP3gZeURbxgfo1av0F5f1+agAsvw6Y13uMeqOTV1C sJwZzKPtS8AIdMJpWp1UtmS5gcZyR9TRwqR0GI+Lf/mB05zDEUgZ3f10aO4fMkpnPdvl hUTZ3zhefsfC9JK0AHbQRDYv+RHwuoY2w7ilCzjvSQwbipELcv50QufxrUsXQgYd3chP Fidw== X-Received: by 10.60.123.112 with SMTP id lz16mr2302768oeb.88.1376432418999; Tue, 13 Aug 2013 15:20:18 -0700 (PDT) Received: from localhost (pool-173-60-222-174.lsanca.fios.verizon.net. [173.60.222.174]) by mx.google.com with ESMTPSA id n2sm41846809obo.6.2013.08.13.15.20.17 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 13 Aug 2013 15:20:18 -0700 (PDT) From: Russ Dill To: linux-omap@vger.kernel.org Cc: devicetree@vger.kernel.org, Kevin Hilman , linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCH v4 2/4] ARM: dts: add AM33XX vdd core opp50 suspend for Beaglebone. Date: Tue, 13 Aug 2013 15:20:10 -0700 Message-Id: <1376432412-8509-3-git-send-email-Russ.Dill@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1376432412-8509-1-git-send-email-Russ.Dill@ti.com> References: <1376432412-8509-1-git-send-email-Russ.Dill@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Changes since v1: * Rebased onto new am335x PM branch This adds a sleep and wake sequence to set the VDD core voltage to the OPP50 level, 0.950V. This saves power during suspend. The sequences are specific to the Beaglebone layout and PMIC, the TPS65217. The sequences are written out by the Cortex-M3. Signed-off-by: Russ Dill --- arch/arm/boot/dts/am335x-bone.dts | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 444b4ed..3f6528d 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -127,10 +127,33 @@ status = "okay"; clock-frequency = <400000>; + /* Set OPP50 (0.95V) for VDD core */ + sleep_sequence = /bits/ 8 < + 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ + 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ + 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ + 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ + 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ + 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ + 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ + 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ + >; + + /* Set OPP100 (1.10V) for VDD core */ + wake_sequence = /bits/ 8 < + 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ + 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ + 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ + 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ + 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ + 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ + 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ + 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ + >; + tps: tps@24 { reg = <0x24>; }; - }; };