| Message ID | 1377286330-29663-3-git-send-email-zonque@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
* Daniel Mack <zonque@gmail.com> [130823 12:39]: > At least the AM33xx SoC has a control module register to configure > details such as the hardware ethernet interface mode. > > I'm not sure whether all SoCs which feature the cpsw block have such a > register, so that third memory region is considered optional for now. Assuming you're talking about omap SCM registers here.. This should be in a separate driver module so the control module parts can eventually be children of the SCM driver as they are really separate devices on the bus. See how the USB PHY parts were done for example. What do these control module registers do? If it's just multiplexing and pinconf, then you can use pinctrl-single,bits most likely for it and access it using the named modes. However, if the register also contains comparators and control for regulators, you should only use pinctrl-single for the multiplexing and pinconf parts. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Monday 26 August 2013 02:34 PM, Tony Lindgren wrote: > * Daniel Mack <zonque@gmail.com> [130823 12:39]: >> At least the AM33xx SoC has a control module register to configure >> details such as the hardware ethernet interface mode. >> >> I'm not sure whether all SoCs which feature the cpsw block have such a >> register, so that third memory region is considered optional for now. > Assuming you're talking about omap SCM registers here.. > > This should be in a separate driver module so the control module > parts can eventually be children of the SCM driver as they are > really separate devices on the bus. See how the USB PHY parts were done > for example. > > What do these control module registers do? If it's just multiplexing > and pinconf, then you can use pinctrl-single,bits most likely for it and > access it using the named modes. > > However, if the register also contains comparators and control for > regulators, you should only use pinctrl-single for the multiplexing > and pinconf parts. > I will take a look into usb control module driver and will try to adopt the driver here also. Regards Mugunthan V N -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index 05d660e..4e5ca54 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -4,7 +4,10 @@ TI SoC Ethernet Switch Controller Device Tree Bindings Required properties: - compatible : Should be "ti,cpsw" - reg : physical base address and size of the cpsw - registers map + registers map. + An optional third memory region can be supplied if + the platform has a control module register to + configure phy interface details - interrupts : property with a value describing the interrupt number - interrupt-parent : The parent interrupt controller diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index fc3263f..485df80 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -372,6 +372,7 @@ struct cpsw_priv { struct cpsw_platform_data data; struct cpsw_ss_regs __iomem *regs; struct cpsw_wr_regs __iomem *wr_regs; + u32 __iomem *gmii_sel_reg; u8 __iomem *hw_stats; struct cpsw_host_regs __iomem *host_port_regs; u32 msg_enable; @@ -1989,6 +1990,16 @@ static int cpsw_probe(struct platform_device *pdev) goto clean_runtime_disable_ret; } + /* Don't fail hard if the optional control memory region is missing */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res) { + priv->gmii_sel_reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->gmii_sel_reg)) { + ret = PTR_ERR(priv->gmii_sel_reg); + goto clean_runtime_disable_ret; + } + } + memset(&dma_params, 0, sizeof(dma_params)); memset(&ale_params, 0, sizeof(ale_params));