From patchwork Tue Sep 17 07:06:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 2901131 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2215E9F1C0 for ; Tue, 17 Sep 2013 07:08:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77D3F20347 for ; Tue, 17 Sep 2013 07:08:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD56720336 for ; Tue, 17 Sep 2013 07:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752249Ab3IQHHw (ORCPT ); Tue, 17 Sep 2013 03:07:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:49158 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752195Ab3IQHHt (ORCPT ); Tue, 17 Sep 2013 03:07:49 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r8H77mae018014; Tue, 17 Sep 2013 02:07:48 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77mWK024356; Tue, 17 Sep 2013 02:07:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 17 Sep 2013 02:07:48 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77maW028570; Tue, 17 Sep 2013 02:07:48 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r8H77kt25073; Tue, 17 Sep 2013 02:07:46 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja Subject: [PATCH 06/11] omapdss: HDMI: Clean up the header files Date: Tue, 17 Sep 2013 12:36:32 +0530 Message-ID: <1379401597-27222-7-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1379401597-27222-1-git-send-email-archit@ti.com> References: <1379401597-27222-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Keep only OMAP4 HDMI core block related structs and enums in ti_hdmi_4xxx_ip.h, move the rest to ti_hdmi.h. This holds all library specific data which will be shared between OMAP4 and OMAP5/DRA7x HDMI encoder drivers. Move the duplicate register read/write/wait_for_bit_change functions in the hdmi library files to ti_hdmi.h Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/hdmi_phy.c | 31 ------ drivers/video/omap2/dss/hdmi_pll.c | 31 ------ drivers/video/omap2/dss/hdmi_wp.c | 31 ------ drivers/video/omap2/dss/ti_hdmi.h | 170 ++++++++++++++++++++++++++++++ drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 31 ------ drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 141 +------------------------ 6 files changed, 171 insertions(+), 264 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi_phy.c b/drivers/video/omap2/dss/hdmi_phy.c index cacd3c4..b79c56b 100644 --- a/drivers/video/omap2/dss/hdmi_phy.c +++ b/drivers/video/omap2/dss/hdmi_phy.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -17,40 +16,10 @@ #include "dss.h" #include "ti_hdmi.h" -#include "ti_hdmi_4xxx_ip.h" #define HDMI_IRQ_LINK_CONNECT (1 << 25) #define HDMI_IRQ_LINK_DISCONNECT (1 << 26) -static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, - u32 val) -{ - __raw_writel(val, base_addr + idx); -} - -static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) -{ - return __raw_readl(base_addr + idx); -} - -#define REG_FLD_MOD(base, idx, val, start, end) \ - hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ - val, start, end)) -#define REG_GET(base, idx, start, end) \ - FLD_GET(hdmi_read_reg(base, idx), start, end) - -static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, - const u16 idx, int b2, int b1, u32 val) -{ - u32 t = 0; - while (val != REG_GET(base_addr, idx, b2, b1)) { - udelay(1); - if (t++ > 10000) - return !val; - } - return val; -} - void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) { #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ diff --git a/drivers/video/omap2/dss/hdmi_pll.c b/drivers/video/omap2/dss/hdmi_pll.c index d53b8e2..cddba76 100644 --- a/drivers/video/omap2/dss/hdmi_pll.c +++ b/drivers/video/omap2/dss/hdmi_pll.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include @@ -18,40 +17,10 @@ #include "dss.h" #include "ti_hdmi.h" -#include "ti_hdmi_4xxx_ip.h" #define HDMI_DEFAULT_REGN 16 #define HDMI_DEFAULT_REGM2 1 -static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, - u32 val) -{ - __raw_writel(val, base_addr + idx); -} - -static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) -{ - return __raw_readl(base_addr + idx); -} - -#define REG_FLD_MOD(base, idx, val, start, end) \ - hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ - val, start, end)) -#define REG_GET(base, idx, start, end) \ - FLD_GET(hdmi_read_reg(base, idx), start, end) - -static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, - const u16 idx, int b2, int b1, u32 val) -{ - u32 t = 0; - while (val != REG_GET(base_addr, idx, b2, b1)) { - udelay(1); - if (t++ > 10000) - return !val; - } - return val; -} - void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) { #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ diff --git a/drivers/video/omap2/dss/hdmi_wp.c b/drivers/video/omap2/dss/hdmi_wp.c index 482940a..7c7f84d 100644 --- a/drivers/video/omap2/dss/hdmi_wp.c +++ b/drivers/video/omap2/dss/hdmi_wp.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -17,36 +16,6 @@ #include "dss.h" #include "ti_hdmi.h" -#include "ti_hdmi_4xxx_ip.h" - -static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, - u32 val) -{ - __raw_writel(val, base_addr + idx); -} - -static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) -{ - return __raw_readl(base_addr + idx); -} - -#define REG_FLD_MOD(base, idx, val, start, end) \ - hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ - val, start, end)) -#define REG_GET(base, idx, start, end) \ - FLD_GET(hdmi_read_reg(base, idx), start, end) - -static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, - const u16 idx, int b2, int b1, u32 val) -{ - u32 t = 0; - while (val != REG_GET(base_addr, idx, b2, b1)) { - udelay(1); - if (t++ > 10000) - return !val; - } - return val; -} void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) { diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h index 107a606..cf096fd 100644 --- a/drivers/video/omap2/dss/ti_hdmi.h +++ b/drivers/video/omap2/dss/ti_hdmi.h @@ -21,7 +21,52 @@ #ifndef _TI_HDMI_H #define _TI_HDMI_H +#include +#include #include +#include