From patchwork Tue Sep 17 07:06:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 2901161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3831EBFF05 for ; Tue, 17 Sep 2013 07:08:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 27AEE20336 for ; Tue, 17 Sep 2013 07:08:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 09DA920348 for ; Tue, 17 Sep 2013 07:08:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752268Ab3IQHH4 (ORCPT ); Tue, 17 Sep 2013 03:07:56 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:34373 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752246Ab3IQHHw (ORCPT ); Tue, 17 Sep 2013 03:07:52 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r8H77pLK018362; Tue, 17 Sep 2013 02:07:51 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77p7x024415; Tue, 17 Sep 2013 02:07:51 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 17 Sep 2013 02:07:51 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77pZs004141; Tue, 17 Sep 2013 02:07:51 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r8H77nt25077; Tue, 17 Sep 2013 02:07:49 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja Subject: [PATCH 07/11] omapdss: HDMI: add HDMI wrapper IRQ flags Date: Tue, 17 Sep 2013 12:36:33 +0530 Message-ID: <1379401597-27222-8-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1379401597-27222-1-git-send-email-archit@ti.com> References: <1379401597-27222-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add flags for the interrupts present in HDMI wrapper block, these will be used to configure HDMI_IRQENABLE_SET/CLEAR and HDMI_IRQSTATUS registers. Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/hdmi_phy.c | 3 --- drivers/video/omap2/dss/ti_hdmi.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi_phy.c b/drivers/video/omap2/dss/hdmi_phy.c index b79c56b..b7d171c 100644 --- a/drivers/video/omap2/dss/hdmi_phy.c +++ b/drivers/video/omap2/dss/hdmi_phy.c @@ -17,9 +17,6 @@ #include "dss.h" #include "ti_hdmi.h" -#define HDMI_IRQ_LINK_CONNECT (1 << 25) -#define HDMI_IRQ_LINK_DISCONNECT (1 << 26) - void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) { #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h index cf096fd..5034080 100644 --- a/drivers/video/omap2/dss/ti_hdmi.h +++ b/drivers/video/omap2/dss/ti_hdmi.h @@ -49,6 +49,21 @@ #define HDMI_WP_AUDIO_CTRL 0x88 #define HDMI_WP_AUDIO_DATA 0x8C +/* HDMI WP IRQ flags */ + +#define HDMI_IRQ_OCP_TIMEOUT (1 << 4) +#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) +#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) +#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10) +#define HDMI_IRQ_VIDEO_VSYNC (1 << 16) +#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17) +#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24) +#define HDMI_IRQ_LINK_CONNECT (1 << 25) +#define HDMI_IRQ_LINK_DISCONNECT (1 << 26) +#define HDMI_IRQ_PLL_LOCK (1 << 29) +#define HDMI_IRQ_PLL_UNLOCK (1 << 30) +#define HDMI_IRQ_PLL_RECAL (1 << 31) + /* HDMI PLL */ #define PLLCTRL_PLL_CONTROL 0x0