From patchwork Wed Oct 9 07:12:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 3007261 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9C8F5BF924 for ; Wed, 9 Oct 2013 07:13:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 85EE820160 for ; Wed, 9 Oct 2013 07:13:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FC0A2017C for ; Wed, 9 Oct 2013 07:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756462Ab3JIHNC (ORCPT ); Wed, 9 Oct 2013 03:13:02 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:47751 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756441Ab3JIHNA (ORCPT ); Wed, 9 Oct 2013 03:13:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r997CbhQ026091; Wed, 9 Oct 2013 02:12:37 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r997CbT6003966; Wed, 9 Oct 2013 02:12:37 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 9 Oct 2013 02:12:36 -0500 Received: from afzal-Latitude-E6420.apr.dhcp.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r997CYAs008302; Wed, 9 Oct 2013 02:12:35 -0500 From: Afzal Mohammed To: , CC: Tony Lindgren Subject: [PATCH v2] ARM: OMAP2+: wakeupgen: AM43x adaptation Date: Wed, 9 Oct 2013 12:42:33 +0530 Message-ID: <1381302753-7045-1-git-send-email-afzal@ti.com> X-Mailer: git-send-email 1.8.3.4 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep default values as earlier, if am43x is detected, update interrupts and banks accordingly. Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen is done only for the single existing cpu, existing code assumes that there are two cpu's. If bitmask is cleared in wakeupgen for the nonexistent second cpu, an imprecise abort happens as soon as Kernel switches to user space. It was rootcaused by Sekhar Nori . Signed-off-by: Afzal Mohammed --- v2: 1. make AM43x adaptation such that changes required for new SoC addition is less 2. avoid usage of am43x local variable, use soc_is_am43xx() instead arch/arm/mach-omap2/omap-wakeupgen.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 813c615..3664562 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -33,8 +33,12 @@ #include "omap4-sar-layout.h" #include "common.h" -#define MAX_NR_REG_BANKS 5 -#define MAX_IRQS 160 +#define AM43XX_NR_REG_BANKS 7 +#define AM43XX_IRQS 224 +#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS +#define MAX_IRQS AM43XX_IRQS +#define DEFAULT_NR_REG_BANKS 5 +#define DEFAULT_IRQS 160 #define WKG_MASK_ALL 0x00000000 #define WKG_UNMASK_ALL 0xffffffff #define CPU_ENA_OFFSET 0x400 @@ -47,8 +51,8 @@ static void __iomem *wakeupgen_base; static void __iomem *sar_base; static DEFINE_RAW_SPINLOCK(wakeupgen_lock); static unsigned int irq_target_cpu[MAX_IRQS]; -static unsigned int irq_banks = MAX_NR_REG_BANKS; -static unsigned int max_irqs = MAX_IRQS; +static unsigned int irq_banks = DEFAULT_NR_REG_BANKS; +static unsigned int max_irqs = DEFAULT_IRQS; static unsigned int omap_secure_apis; /* @@ -418,12 +422,16 @@ int __init omap_wakeupgen_init(void) irq_banks = OMAP4_NR_BANKS; max_irqs = OMAP4_NR_IRQS; omap_secure_apis = 1; + } else if (soc_is_am43xx()) { + irq_banks = AM43XX_NR_REG_BANKS; + max_irqs = AM43XX_IRQS; } /* Clear all IRQ bitmasks at wakeupGen level */ for (i = 0; i < irq_banks; i++) { wakeupgen_writel(0, i, CPU0_ID); - wakeupgen_writel(0, i, CPU1_ID); + if (!soc_is_am43xx()) + wakeupgen_writel(0, i, CPU1_ID); } /*