From patchwork Tue Oct 15 17:52:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 3047021 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 03C3D9F2B6 for ; Tue, 15 Oct 2013 17:53:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2AF920259 for ; Tue, 15 Oct 2013 17:53:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA9FF2042A for ; Tue, 15 Oct 2013 17:53:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933617Ab3JORxA (ORCPT ); Tue, 15 Oct 2013 13:53:00 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:37199 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933185Ab3JORw7 (ORCPT ); Tue, 15 Oct 2013 13:52:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r9FHqwL1003321; Tue, 15 Oct 2013 12:52:58 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r9FHqvD6024281; Tue, 15 Oct 2013 12:52:58 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 15 Oct 2013 12:52:57 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r9FHqt8g030529; Tue, 15 Oct 2013 12:52:56 -0500 From: Pekon Gupta To: CC: , , Pekon Gupta Subject: [PATCH 1/1] arm: omap: gpmc: remove detection of ecc-capability based on SoC name Date: Tue, 15 Oct 2013 23:22:39 +0530 Message-ID: <1381859559-15281-1-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Legacy OMAP SoC like OMAP2xxx, OMAP3xxx do not have in-build ELM h/w engine, so they cannot support h/w based BCH ECC error-detection. Thus, gpmc_hwecc_bch_capable() check was added in following commit to find-out which SoC have in-built ELM h/w to support hardware based ecc-correction. commit 3852ccd66a9bcb2aa6f46bce5442b6d8d08e5b5d Author: Afzal Mohammed AuthorDate: 2012-10-01 But with DT based kernel, presence of ELM h/w engine on SoC is parsed from DT data part of .dtsi file, which is unique for each device. Hence hard-coded check for each device can be dropped. Signed-off-by: Pekon Gupta --- arch/arm/mach-omap2/gpmc-nand.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 662c7fd..2b03eba 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -43,28 +43,6 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) -{ - /* support only OMAP3 class */ - if (!cpu_is_omap34xx() && !soc_is_am33xx()) { - pr_err("BCH ecc is not supported on this CPU\n"); - return 0; - } - - /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 - * and AM33xx derivates. Other chips may be added if confirmed to work. - */ - if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && - (!soc_is_am33xx())) { - pr_err("BCH 4-bit mode is not supported on this CPU\n"); - return 0; - } - - return 1; -} - int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -127,9 +105,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) - return -EINVAL; - err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n");