From patchwork Mon Nov 11 20:06:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Fenkart X-Patchwork-Id: 3169541 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 19B889F522 for ; Mon, 11 Nov 2013 20:09:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ECAAB203F3 for ; Mon, 11 Nov 2013 20:09:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAF16203AF for ; Mon, 11 Nov 2013 20:09:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752625Ab3KKUJ3 (ORCPT ); Mon, 11 Nov 2013 15:09:29 -0500 Received: from mail-ee0-f54.google.com ([74.125.83.54]:41805 "EHLO mail-ee0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751036Ab3KKUJ1 (ORCPT ); Mon, 11 Nov 2013 15:09:27 -0500 Received: by mail-ee0-f54.google.com with SMTP id c50so2712868eek.13 for ; Mon, 11 Nov 2013 12:09:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=696k9hHcvlUpdGZLaRlczivyGCaQa2t9uvNu+m2ShWI=; b=MHYjC4w3CqGaefs4FQWzY6kyQ7ncfPSL9sFkZV0eVb53SuhM0I3Laz962swmsK9pXk D4uR/bXnghHOST9k90AFhdKV0N67vEy8xlqyVOFvi3HYBdk/cNXY5sIrtz31bkptGyzG lK399LpB+VrfvDSFEzEaPV35dViW/v/Hs2D3EBok2aPMJSiiNCPy75Dk/ecVDpINqDyF 7YCgojrQMgMfUZHXuOTMdzurjZwVoa5U+5oU0RLB2d+finLDGN1slL6eeUJmNBArfWqD Dfuah7ihuliwWSb9bI3uVtIYF/LbcB62VAnqRQLSHriwyQDNMEBXgrVzRe3XGxISmNmz XOfQ== X-Received: by 10.14.108.9 with SMTP id p9mr37367455eeg.8.1384200565990; Mon, 11 Nov 2013 12:09:25 -0800 (PST) Received: from localhost (cust.static.84-253-15-149.cybernet.ch. [84.253.15.149]) by mx.google.com with ESMTPSA id s3sm66931493eeo.3.2013.11.11.12.09.21 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 11 Nov 2013 12:09:25 -0800 (PST) From: Andreas Fenkart To: Chris Ball Cc: Tony Lindgren , Grant Likely , Felipe Balbi , Balaji T K , zonque@gmail.com, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org, Andreas Fenkart Subject: [PATCH 1/3] mmc: omap_hsmmc: Enable SDIO IRQ. Date: Mon, 11 Nov 2013 21:06:43 +0100 Message-Id: <1384200405-8402-2-git-send-email-afenkart@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1384200405-8402-1-git-send-email-afenkart@gmail.com> References: <1384200405-8402-1-git-send-email-afenkart@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For now, only support SDIO interrupt if we are booted with DT. This is because some platforms need special quirks. And we don't want to add new legacy mux platform init code callbacks any longer as we are moving to DT based booting anyways. Broken hardware, missing the swakueup line, should fallback to polling, by setting 'ti,quirk-swakup-missing' in the device tree. Otherwise pending SDIO IRQ are not detected while in suspend. This affects am33xx processors. For the DT-Binding portion: Reviewed-by: Grant Likely Acked-by: Kumar Gala Signed-off-by: Andreas Fenkart --- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 18 ++++ drivers/mmc/host/omap_hsmmc.c | 86 ++++++++++++++++++-- 2 files changed, 95 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index ed271fc..1136e6b 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -20,6 +20,24 @@ ti,dual-volt: boolean, supports dual voltage cards ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed +ti,quirk-swakup-missing: SOC missing the swakeup line, will not detect +SDIO irq while in suspend. Fallback to polling. Affected chips are +am335x, + + ------ + | PRCM | + ------ + ^ | + swakeup | | fclk + | v + ------ ------- ----- + | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | + ------ ------- ----- + +In suspend the fclk is off and the module is disfunctional. Even +register reads will fail. A small logic in the host will request fclk +restore, when an external event is detected. Once the clock is +restored, the host detects the event normally. Example: mmc1: mmc@0x4809c000 { diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index b392130..6b0ec55 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -130,6 +130,7 @@ static void apply_clk_hack(struct device *dev) #define TC_EN (1 << 1) #define BWR_EN (1 << 4) #define BRR_EN (1 << 5) +#define CIRQ_EN (1 << 8) #define ERR_EN (1 << 15) #define CTO_EN (1 << 16) #define CCRC_EN (1 << 17) @@ -210,6 +211,9 @@ struct omap_hsmmc_host { int reqs_blocked; int use_reg; int req_in_progress; + int flags; +#define HSMMC_SDIO_IRQ_ENABLED (1 << 0) /* SDIO irq enabled */ + struct omap_hsmmc_next next_data; struct omap_mmc_platform_data *pdata; }; @@ -490,27 +494,40 @@ static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, struct mmc_command *cmd) { - unsigned int irq_mask; + u32 irq_mask = INT_EN_MASK; + unsigned long flags; if (host->use_dma) - irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); - else - irq_mask = INT_EN_MASK; + irq_mask &= ~(BRR_EN | BWR_EN); /* Disable timeout for erases */ if (cmd->opcode == MMC_ERASE) irq_mask &= ~DTO_EN; + spin_lock_irqsave(&host->irq_lock, flags); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + + /* latch pending CIRQ, but don't signal */ + if (host->flags & HSMMC_SDIO_IRQ_ENABLED) + irq_mask |= CIRQ_EN; OMAP_HSMMC_WRITE(host->base, IE, irq_mask); + spin_unlock_irqrestore(&host->irq_lock, flags); } static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) { - OMAP_HSMMC_WRITE(host->base, ISE, 0); - OMAP_HSMMC_WRITE(host->base, IE, 0); + u32 irq_mask = 0; + unsigned long flags; + + spin_lock_irqsave(&host->irq_lock, flags); + /* no transfer running, need to signal cirq if enabled */ + if (host->flags & HSMMC_SDIO_IRQ_ENABLED) + irq_mask |= CIRQ_EN; + OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + OMAP_HSMMC_WRITE(host->base, IE, irq_mask); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); + spin_unlock_irqrestore(&host->irq_lock, flags); } /* Calculate divisor for the given clock frequency */ @@ -1067,8 +1084,12 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) int status; status = OMAP_HSMMC_READ(host->base, STAT); - while (status & INT_EN_MASK && host->req_in_progress) { - omap_hsmmc_do_irq(host, status); + while (status & (INT_EN_MASK | CIRQ_EN)) { + if (host->req_in_progress) + omap_hsmmc_do_irq(host, status); + + if (status & CIRQ_EN) + mmc_signal_sdio_irq(host->mmc); /* Flush posted write */ status = OMAP_HSMMC_READ(host->base, STAT); @@ -1583,6 +1604,37 @@ static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) mmc_slot(host).init_card(card); } +static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct omap_hsmmc_host *host = mmc_priv(mmc); + u32 irq_mask; + unsigned long flags; + + spin_lock_irqsave(&host->irq_lock, flags); + + irq_mask = OMAP_HSMMC_READ(host->base, ISE); + if (enable) { + host->flags |= HSMMC_SDIO_IRQ_ENABLED; + irq_mask |= CIRQ_EN; + } else { + host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; + irq_mask &= ~CIRQ_EN; + } + OMAP_HSMMC_WRITE(host->base, IE, irq_mask); + + /* + * if enable, piggy back detection on current request + * but always disable immediately + */ + if (!host->req_in_progress || !enable) + OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); + + /* flush posted write */ + OMAP_HSMMC_READ(host->base, IE); + + spin_unlock_irqrestore(&host->irq_lock, flags); +} + static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) { u32 hctl, capa, value; @@ -1635,7 +1687,7 @@ static const struct mmc_host_ops omap_hsmmc_ops = { .get_cd = omap_hsmmc_get_cd, .get_ro = omap_hsmmc_get_ro, .init_card = omap_hsmmc_init_card, - /* NYET -- enable_sdio_irq */ + .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, }; #ifdef CONFIG_DEBUG_FS @@ -2021,6 +2073,22 @@ static int omap_hsmmc_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "pins are not configured from the driver\n"); + /* + * For now, only support SDIO interrupt if we are booted with + * DT. This is because some platforms need special quirks. And + * we don't want to add new legacy mux platform init code + * callbacks any longer as we are moving to DT based booting + * anyways. + */ + if (pdev->dev.of_node) { + mmc->caps |= MMC_CAP_SDIO_IRQ; + if (of_find_property(host->dev->of_node, + "ti,quirk-swakeup-missing", NULL)) { + /* no wakeup from deeper power states, use polling */ + mmc->caps &= ~MMC_CAP_SDIO_IRQ; + } + } + omap_hsmmc_protect_card(host); mmc_add_host(mmc);