From patchwork Wed Nov 27 13:56:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 3248121 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0B5299F3A0 for ; Wed, 27 Nov 2013 13:56:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C5A32205CD for ; Wed, 27 Nov 2013 13:56:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 818EE205D3 for ; Wed, 27 Nov 2013 13:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754586Ab3K0N4U (ORCPT ); Wed, 27 Nov 2013 08:56:20 -0500 Received: from mail-ea0-f171.google.com ([209.85.215.171]:39750 "EHLO mail-ea0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752668Ab3K0N4T (ORCPT ); Wed, 27 Nov 2013 08:56:19 -0500 Received: by mail-ea0-f171.google.com with SMTP id h10so4773906eak.16 for ; Wed, 27 Nov 2013 05:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=I7ZLLLOlCKoa3ohgyDfvdmC4iMgrGwySmx17XmU0X/A=; b=mTGS4C3RMBlNAFUjVrVFUSLlXAkoy6du8HizQgbtCDrGwLvp+4+Y8i3ih9bP44mRHW YidkpD1PEYtnewQD9Wx6OtaW+VmJ8fHtne3mjwn2BarpbuoYmf3RQ47sF4ozp+HqJunY 8HfEq0sQRqMuwlnXfM5XPTHV9HoBzTZRY1vfGN+VJRmWkgbiog56YgdKGi+ixqNU01IX A/6jiV/RZeS8B+AeccdVVDbUv07w2bEGlpc9hHrT1JOpvZNqMJvz9AfG9gj/LGwD4kbB YOaO4r0eR5E+v3hgpRcQ1ApxZ+duiSQfPIgcJ1iYr5SDBTyXMh0cN8dAdf1bpNNtsHX8 5ruA== X-Received: by 10.15.108.73 with SMTP id cc49mr6407eeb.93.1385560578451; Wed, 27 Nov 2013 05:56:18 -0800 (PST) Received: from tamtam.Speedport_W_723V_1_32_000 (pd907dbf4.dip0.t-ipconnect.de. [217.7.219.244]) by mx.google.com with ESMTPSA id e43sm8949720eep.7.2013.11.27.05.56.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Nov 2013 05:56:17 -0800 (PST) From: Daniel Mack To: nsekhar@ti.com, linux-omap@vger.kernel.org, joelf@ti.com, gururaja.hebbar@ti.com, balajitk@ti.com Cc: s.neumann@raumfeld.com, Russ.Dill@ti.com, nm@ti.com, vaibhav.bedia@gmail.com, linux-arm-kernel@lists.infradead.org, khilman@linaro.org, Daniel Mack Subject: [PATCH v7] ARM: omap: edma: add suspend suspend/resume hooks Date: Wed, 27 Nov 2013 14:56:11 +0100 Message-Id: <1385560571-3939-1-git-send-email-zonque@gmail.com> X-Mailer: git-send-email 1.8.4.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch makes the edma driver resume correctly after suspend. Tested on an AM33xx platform with cyclic audio streams and omap_hsmmc. All information can be reconstructed by already known runtime information. As we now use some functions that were previously only used from __init context, annotations had to be dropped. [nm@ti.com: added error handling for runtime + suspend_late/early_resume] Signed-off-by: Nishanth Menon Signed-off-by: Daniel Mack Tested-by: Joel Fernandes Acked-by: Joel Fernandes --- v6 -> v7: * Addressed comments from Sekhar Nori: * pm_runtime_get_sync() returns negative errors, so do not use IS_ERR_VALUE() * Several style fixes arch/arm/common/edma.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 92 insertions(+), 3 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 41bca32..dece66d 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -239,6 +239,8 @@ struct edma { /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; + struct edma_soc_info *info; + /* The edma_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ @@ -290,13 +292,13 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, ~(0x7 << bit), queue_no << bit); } -static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) +static void map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { int bit = queue_no * 4; edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } -static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, +static void assign_priority_to_queue(unsigned ctlr, int queue_no, int priority) { int bit = queue_no * 4; @@ -315,7 +317,7 @@ static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, * included in that particular EDMA variant (Eg : dm646x) * */ -static void __init map_dmach_param(unsigned ctlr) +static void map_dmach_param(unsigned ctlr) { int i; for (i = 0; i < EDMA_MAX_DMACH; i++) @@ -1785,15 +1787,102 @@ static int edma_probe(struct platform_device *pdev) edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); edma_write_array(j, EDMA_QRAE, i, 0x0); } + edma_cc[j]->info = info[j]; arch_num_cc++; } return 0; } +static int edma_pm_suspend(struct device *dev) +{ + int j, r; + + r = pm_runtime_get_sync(dev); + if (r < 0) { + dev_err(dev, "%s: get_sync returned %d\n", __func__, r); + return r; + } + + for (j = 0; j < arch_num_cc; j++) { + struct edma *ecc = edma_cc[j]; + + disable_irq(ecc->irq_res_start); + disable_irq(ecc->irq_res_end); + } + + pm_runtime_put_sync(dev); + + return 0; +} + +static int edma_pm_resume(struct device *dev) +{ + int i, j, r; + + r = pm_runtime_get_sync(dev); + if (r < 0) { + dev_err(dev, "%s: get_sync returned %d\n", __func__, r); + return r; + } + + for (j = 0; j < arch_num_cc; j++) { + struct edma *cc = edma_cc[j]; + + s8 (*queue_priority_mapping)[2]; + s8 (*queue_tc_mapping)[2]; + + queue_tc_mapping = cc->info->queue_tc_mapping; + queue_priority_mapping = cc->info->queue_priority_mapping; + + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(j, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(j, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* + * Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(j); + + for (i = 0; i < cc->num_channels; i++) { + if (test_bit(i, cc->edma_inuse)) { + /* ensure access through shadow region 0 */ + edma_or_array2(j, EDMA_DRAE, 0, i >> 5, + BIT(i & 0x1f)); + + setup_dma_interrupt(i, + cc->intr_data[i].callback, + cc->intr_data[i].data); + } + } + + enable_irq(cc->irq_res_start); + enable_irq(cc->irq_res_end); + } + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops edma_pm_ops = { + .suspend_late = edma_pm_suspend, + .resume_early = edma_pm_resume, +}; + static struct platform_driver edma_driver = { .driver = { .name = "edma", + .pm = &edma_pm_ops, .of_match_table = edma_of_ids, }, .probe = edma_probe,