From patchwork Tue Dec 17 11:10:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 3360671 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B988C0D4A for ; Tue, 17 Dec 2013 11:10:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BABB02034F for ; Tue, 17 Dec 2013 11:10:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74AB9202E9 for ; Tue, 17 Dec 2013 11:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752808Ab3LQLK3 (ORCPT ); Tue, 17 Dec 2013 06:10:29 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:48156 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752073Ab3LQLK2 (ORCPT ); Tue, 17 Dec 2013 06:10:28 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id rBHBASR3024042; Tue, 17 Dec 2013 05:10:28 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBHBASgh010968; Tue, 17 Dec 2013 05:10:28 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 17 Dec 2013 05:10:27 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBHBAR4c001826; Tue, 17 Dec 2013 05:10:27 -0600 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id rBHBAPt20692; Tue, 17 Dec 2013 05:10:26 -0600 (CST) From: Archit Taneja To: CC: , , Archit Taneja Subject: [PATCH] omapdss: dispc: Preload more data in pipeline DMAs for OMAP4+ SoCs Date: Tue, 17 Dec 2013 16:40:21 +0530 Message-ID: <1387278621-10966-1-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/dispc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 6578540..ace179e 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -90,6 +90,8 @@ struct dispc_features { /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ bool mstandby_workaround:1; + + bool set_max_preload:1; }; #define DISPC_MAX_NR_FIFOS 5 @@ -1200,6 +1202,15 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), FLD_VAL(high, hi_start, hi_end) | FLD_VAL(low, lo_start, lo_end)); + + /* + * configure the preload to the pipeline's high threhold, if HT it's too + * large for the preload field, set the threshold to the maximum value + * that can be held by the preload register + */ + if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && + plane != OMAP_DSS_WB) + dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfff)); } EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold); @@ -3525,6 +3536,7 @@ static const struct dispc_features omap24xx_dispc_feats __initconst = { .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, .no_framedone_tv = true, + .set_max_preload = false, }; static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { @@ -3544,6 +3556,7 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, .no_framedone_tv = true, + .set_max_preload = false, }; static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { @@ -3563,6 +3576,7 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, .no_framedone_tv = true, + .set_max_preload = false, }; static const struct dispc_features omap44xx_dispc_feats __initconst = { @@ -3582,6 +3596,7 @@ static const struct dispc_features omap44xx_dispc_feats __initconst = { .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, .gfx_fifo_workaround = true, + .set_max_preload = true, }; static const struct dispc_features omap54xx_dispc_feats __initconst = { @@ -3602,6 +3617,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = { .num_fifos = 5, .gfx_fifo_workaround = true, .mstandby_workaround = true, + .set_max_preload = true, }; static int __init dispc_init_features(struct platform_device *pdev)