From patchwork Tue Jan 21 19:47:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Fritz X-Patchwork-Id: 3519421 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8B656C02DC for ; Tue, 21 Jan 2014 19:48:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7131020117 for ; Tue, 21 Jan 2014 19:48:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54B7320109 for ; Tue, 21 Jan 2014 19:48:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750957AbaAUTsS (ORCPT ); Tue, 21 Jan 2014 14:48:18 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:41631 "EHLO mail-la0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752353AbaAUTsQ (ORCPT ); Tue, 21 Jan 2014 14:48:16 -0500 Received: by mail-la0-f45.google.com with SMTP id b8so7035807lan.32 for ; Tue, 21 Jan 2014 11:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NSsTVQX4GHUa/g5poUZKawCKkHTkJx7dzTpTyJtmazA=; b=0YKA2gL7OGYI2VBsGIwwsX6BEPhBAmHN29Kt+dKLvXmqYYpYEDLH9PCdSGiTRwJZvY tPX55eVoYwKi4s6Iq3rw2Ups8hjwEgKEEiZ6CLmQRcXwT3wu7HnF8fUVc4JkNa8GOcTV AhsGoT5V/OfY0jNjTPpn/5RI1mSIr3wYhSAaMaXqMVbSp8wSdi7Jr9xHmKRAzde9C7KG 3I6ZBqScX6VEXeeGyO4Gj415R/H/W/1uPyA4pHWshBWlnN4hNwPNnsbcJFiG6oUfe/sL EL7zOhwJ9O8yNbi409xxaalHX5XSA3L2pBNTYHRs8LYovcn1AmQEk+Ve3iy1Pyt1bTmw bFyg== X-Received: by 10.152.19.133 with SMTP id f5mr2258697lae.52.1390333695063; Tue, 21 Jan 2014 11:48:15 -0800 (PST) Received: from mars.ipredator.se (anon-35-60.vpn.ipredator.se. [46.246.35.60]) by mx.google.com with ESMTPSA id n13sm5015606lbl.17.2014.01.21.11.48.12 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Jan 2014 11:48:14 -0800 (PST) From: Christoph Fritz To: Tony Lindgren , Tomi Valkeinen , Mark Rutland , Ian Campbell , , Archit Taneja , Javier Martinez Canillas , Daniel Mack , "Hans J. Koch" Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH 3/6] ARM: dts: omap3: Add support for INCOstartec DBB056 baseboard Date: Tue, 21 Jan 2014 20:47:37 +0100 Message-Id: <1390333660-30573-4-git-send-email-chf.fritz@googlemail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390333660-30573-1-git-send-email-chf.fritz@googlemail.com> References: <1390333660-30573-1-git-send-email-chf.fritz@googlemail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP INCOstartec LILLY-DBB056 is a carrier board (baseboard) for computer-on-module LILLY-A83X. This patch adds device-tree support for most of its features. Signed-off-by: Christoph Fritz --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap3-lilly-dbb056.dts | 160 ++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-lilly-dbb056.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..e0adfa9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -186,6 +186,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-gta04.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ + omap3-lilly-dbb056.dtb \ omap3-zoom3.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts new file mode 100644 index 0000000..b063b72 --- /dev/null +++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2014 Christoph Fritz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +/dts-v1/; + +#include "omap3-lilly-a83x.dtsi" + +/ { + model = "INCOstartec LILLY-DBB056 (DM3730)"; + compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3"; +}; + +&twl { + vaux2: regulator-vaux2 { + compatible = "ti,twl4030-vaux2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + lan9117_pins: pinmux_lan9117_pins { + pinctrl-single,pins = < + 0xe4 (PIN_INPUT | MUX_MODE4) /* gpio_98 */ + >; + }; + + gpio4_pins: pinmux_gpio4_pins { + pinctrl-single,pins = < + 0xfe (PIN_INPUT | MUX_MODE4) /* gpio_111 -> sja1000 IRQ */ + >; + }; + + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x15c (PIN_OUTPUT | MUX_MODE4) /* gpio_156 -> enable DSS */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + 0x134 (PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + 0x136 (PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + 0x138 (PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + 0x13a (PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ + 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_163 -> wp */ + 0x16c (PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_164 -> cd */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + 0x198 (PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + 0x19a (PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + 0x19c (PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + 0x19e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; +}; + +&mmc2 { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc1>; + cd-gpios = <&gpio6 4 0>; /* gpio_164 */ + wp-gpios = <&gpio6 3 0>; /* gpio_163 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + ti,dual-volt; +}; + +&mcspi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ + <4 0 0x20000000 0x01000000>, + <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <10>; + gpmc,cs-rd-off-ns = <65>; + gpmc,cs-wr-off-ns = <65>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <65>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <65>; + gpmc,rd-cycle-ns = <100>; + gpmc,wr-cycle-ns = <100>; + gpmc,access-ns = <60>; + gpmc,page-burst-access-ns = <5>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wr-data-mux-bus-ns = <15>; + gpmc,wr-access-ns = <75>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <®_vcc3>; + vdd33a-supply = <®_vcc3>; + reg-io-width = <4>; + interrupt-parent = <&gpio4>; + interrupts = <2 0x2>; + reg = <4 0 0xff>; + pinctrl-names = "default"; + pinctrl-0 = <&lan9117_pins>; + phy-mode = "mii"; + smsc,force-internal-phy; + }; +};